NXP Semiconductors MKW36Z4 2024.06.02 MKW36Z4 NXP Microcontroller CM0PLUS r0p0 little 2 false 8 32 ADC0 Analog-to-Digital Converter ADC0 0x0 0x0 0x70 registers n ADC0 15 CFG1 ADC Configuration Register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2(BUSCLK/2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 CFG2 ADC Configuration Register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux Select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write n 0x0 0x0 CLM0 Calibration Value 0 6 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write n 0x0 0x0 CLM1 Calibration Value 0 7 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write n 0x0 0x0 CLM2 Calibration Value 0 8 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write n 0x0 0x0 CLM3 Calibration Value 0 9 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write n 0x0 0x0 CLM4 Calibration Value 0 10 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write n 0x0 0x0 CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write n 0x0 0x0 CLMS Calibration Value 0 6 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write n 0x0 0x0 CLP0 Calibration Value 0 6 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write n 0x0 0x0 CLP1 Calibration Value 0 7 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write n 0x0 0x0 CLP2 Calibration Value 0 8 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write n 0x0 0x0 CLP3 Calibration Value 0 9 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write n 0x0 0x0 CLP4 Calibration Value 0 10 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write n 0x0 0x0 CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write n 0x0 0x0 CLPS Calibration Value 0 6 read-write CV1 Compare Value Registers 0x30 32 read-write n 0x0 0x0 CV Compare Value. 0 16 read-write CV2 Compare Value Registers 0x4C 32 read-write n 0x0 0x0 CV Compare Value. 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write n 0x0 0x0 MG Minus-Side Gain 0 16 read-write OFS ADC Offset Correction Register 0x28 32 read-write n 0x0 0x0 OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write n 0x0 0x0 PG Plus-Side Gain 0 16 read-write RA ADC Data Result Register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RB ADC Data Result Register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only SC1A ADC Status and Control Registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC1B ADC Status and Control Registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC2 Status and Control Register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 SC3 Status and Control Register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 BTLE_RF BTLE_RF BTLE_RF 0x0 0x600 0xE registers n BLE_FSM BLE STATE MACHINE STATUS 0x60C 16 read-only n 0x0 0x0 BTLE_RX_EN BLE RX Enable Control to TSM 6 1 read-only BTLE_TX_EN BLE TX Enable Control to TSM 5 1 read-only RX_CS BLE RX State Machine Current State 12 4 read-only TX_CS BLE TX State Machine Current State 7 5 read-only VAR_CS Variable State Machine Current State 0 5 read-only BLE_PART_ID BLUETOOTH LOW ENERGY PART ID 0x600 16 read-only n 0x0 0x0 BLE_PART_ID BLE Part ID 0 16 read-only 0 Pre-production #0 1 Pre-production #1 2 KW40 #10 4 K3S #100 5 KW35/KW36 #101 3 KW41 #11 DSM_STATUS BLE DSM STATUS 0x604 16 read-only n 0x0 0x0 ORF_SYSCLK_REQ RF Oscillator Requested 0 1 read-only RIF_LL_ACTIVE Link Layer Active 1 1 read-only XCVR_BUSY Transceiver Busy Status Bit 2 1 read-only 0 RF Channel in available (TSM is idle) #0 1 RF Channel in use (TSM is busy) #1 MISC_CTRL BLE MISCELLANEOUS CONTROL 0x608 16 read-write n 0x0 0x0 BLE_FSM_SEL BLE FSM Selector 2 3 read-write TSM_INTR_EN TSM Interrupt Enable 1 1 read-write CAN0 CAN CAN0 0x0 0x0 0xC0C registers n CBT CAN Bit Timing Register 0x50 32 read-write n 0x0 0x0 BTF Bit Timing Format Enable 31 1 read-write 0 Extended bit time definitions disabled. #0 1 Extended bit time definitions enabled. #1 EPRESDIV Extended Prescaler Division Factor 21 10 read-write EPROPSEG Extended Propagation Segment 10 6 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPSEG2 Extended Phase Segment 2 0 5 read-write ERJW Extended Resync Jump Width 16 5 read-write CRCR CRC Register 0x44 32 read-only n 0x0 0x0 MBCRC CRC Mailbox 16 7 read-only TXCRC Transmitted CRC value 0 15 read-only CS0 Message Buffer 0 CS Register CAN0 0x80 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS1 Message Buffer 1 CS Register CAN0 0x90 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS10 Message Buffer 10 CS Register CAN0 0x120 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS11 Message Buffer 11 CS Register CAN0 0x130 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS12 Message Buffer 12 CS Register CAN0 0x140 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS13 Message Buffer 13 CS Register CAN0 0x150 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS14 Message Buffer 14 CS Register CAN0 0x160 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS15 Message Buffer 15 CS Register CAN0 0x170 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS16 Message Buffer 16 CS Register CAN0 0x180 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS17 Message Buffer 17 CS Register CAN0 0x190 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS18 Message Buffer 18 CS Register CAN0 0x1A0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS19 Message Buffer 19 CS Register CAN0 0x1B0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS2 Message Buffer 2 CS Register CAN0 0xA0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS20 Message Buffer 20 CS Register CAN0 0x1C0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS21 Message Buffer 21 CS Register CAN0 0x1D0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS22 Message Buffer 22 CS Register CAN0 0x1E0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS23 Message Buffer 23 CS Register CAN0 0x1F0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS24 Message Buffer 24 CS Register CAN0 0x200 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS25 Message Buffer 25 CS Register CAN0 0x210 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS26 Message Buffer 26 CS Register CAN0 0x220 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS27 Message Buffer 27 CS Register CAN0 0x230 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS28 Message Buffer 28 CS Register CAN0 0x240 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS29 Message Buffer 29 CS Register CAN0 0x250 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS3 Message Buffer 3 CS Register CAN0 0xB0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS30 Message Buffer 30 CS Register CAN0 0x260 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS31 Message Buffer 31 CS Register CAN0 0x270 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS4 Message Buffer 4 CS Register CAN0 0xC0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS5 Message Buffer 5 CS Register CAN0 0xD0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS6 Message Buffer 6 CS Register CAN0 0xE0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS7 Message Buffer 7 CS Register CAN0 0xF0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS8 Message Buffer 8 CS Register CAN0 0x100 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS9 Message Buffer 9 CS Register CAN0 0x110 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CTRL1 Control 1 register 0x4 32 read-write n 0x0 0x0 BOFFMSK Bus Off Interrupt Mask 15 1 read-write 0 Bus Off interrupt disabled. #0 1 Bus Off interrupt enabled. #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled. #0 1 Automatic recovering from Bus Off state disabled. #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Interrupt Mask 14 1 read-write 0 Error interrupt disabled. #0 1 Error interrupt enabled. #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 LOM Listen-Only Mode 3 1 read-write 0 Listen-Only mode is deactivated. #0 1 FlexCAN module operates in Listen-Only mode. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled. #0 1 Loop Back enabled. #1 PRESDIV Prescaler Division Factor 24 8 read-write PROPSEG Propagation Segment 0 3 read-write PSEG1 Phase Segment 1 19 3 read-write PSEG2 Phase Segment 2 16 3 read-write RJW Resync Jump Width 22 2 read-write RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled. #0 1 Rx Warning Interrupt enabled. #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples a majority rule is used. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled. #0 1 Tx Warning Interrupt enabled. #1 CTRL2 Control 2 register 0x34 32 read-write n 0x0 0x0 BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write 0 Bus Off Done interrupt disabled. #0 1 Bus Off Done interrupt enabled. #1 EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 EDFLTDIS Edge Filter Disable 11 1 read-write 0 Edge Filter is enabled. #0 1 Edge Filter is disabled. #1 ERRMSK_FAST Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames 31 1 read-write 0 ERRINT_FAST Error interrupt disabled. #0 1 ERRINT_FAST Error interrupt enabled. #1 ISOCANFDEN ISO CAN FD Enable 12 1 read-write 0 FlexCAN operates using the non-ISO CAN FD protocol. #0 1 FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 PREXCEN Protocol Exception Enable 14 1 read-write 0 Protocol Exception is disabled. #0 1 Protocol Exception is enabled. #1 RFFN Number Of Rx FIFO Filters 24 4 read-write RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 TASD Tx Arbitration Start Delay 19 5 read-write TIMER_SRC Timer Source 15 1 read-write 0 The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. #0 1 The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device specific section for details about the external time tick. #1 ECR Error Counter 0x1C 32 read-write n 0x0 0x0 RXERRCNT Receive Error Counter 8 8 read-write RXERRCNT_FAST Receive Error Counter for fast bits 24 8 read-write TXERRCNT Transmit Error Counter 0 8 read-write TXERRCNT_FAST Transmit Error Counter for fast bits 16 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write n 0x0 0x0 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence. #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT0ERR_FAST Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 30 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 BIT1ERR_FAST Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 31 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write 0 No such occurrence. #0 1 FlexCAN module has completed Bus Off process. #1 BOFFINT Bus Off Interrupt 2 1 read-write 0 No such occurrence. #0 1 FlexCAN module entered Bus Off state. #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 CRCERR_FAST Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 28 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit in the Error and Status Register. #1 ERRINT_FAST Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set 20 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. #1 ERROVR Error Overrun bit 21 1 read-write 0 Overrun has not occurred. #0 1 Overrun has occurred. #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 FRMERR Form Error 11 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 FRMERR_FAST Form Error in the Data Phase of CAN FD frames with the BRS bit set 27 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 IDLE IDLE 7 1 read-only 0 No such occurrence. #0 1 CAN bus is now IDLE. #1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence. #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 RX FlexCAN In Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence. #0 1 RXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 STFERR_FAST Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 26 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence. #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 TX FlexCAN In Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence. #0 1 TXERRCNT is greater than or equal to 96. #1 WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence. #0 1 Indicates a recessive to dominant transition was received on the CAN bus. #1 ESR2 Error and Status 2 register 0x38 32 read-only n 0x0 0x0 IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 FDCBT CAN FD Bit Timing Register 0xC04 32 read-write n 0x0 0x0 FPRESDIV Fast Prescaler Division Factor 20 10 read-write FPROPSEG Fast Propagation Segment 10 5 read-write FPSEG1 Fast Phase Segment 1 5 3 read-write FPSEG2 Fast Phase Segment 2 0 3 read-write FRJW Fast Resync Jump Width 16 3 read-write FDCRC CAN FD CRC Register 0xC08 32 read-only n 0x0 0x0 FD_MBCRC CRC Mailbox Number for FD_TXCRC 24 7 read-only FD_TXCRC Extended Transmitted CRC value 0 21 read-only FDCTRL CAN FD Control Register 0xC00 32 read-write n 0x0 0x0 FDRATE Bit Rate Switch Enable 31 1 read-write 0 Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. #0 1 Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. #1 MBDSR0 Message Buffer Data Size for Region 0 16 2 read-write 00 Selects 8 bytes per Message Buffer. #00 01 Selects 16 bytes per Message Buffer. #01 10 Selects 32 bytes per Message Buffer. #10 11 Selects 64 bytes per Message Buffer. #11 TDCEN Transceiver Delay Compensation Enable 15 1 read-write 0 TDC is disabled #0 1 TDC is enabled #1 TDCFAIL Transceiver Delay Compensation Fail 14 1 read-write 0 Measured loop delay is in range. #0 1 Measured loop delay is out of range. #1 TDCOFF Transceiver Delay Compensation Offset 8 5 read-write TDCVAL Transceiver Delay Compensation Value 0 6 read-only ID0 Message Buffer 0 ID Register CAN0 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID1 Message Buffer 1 ID Register CAN0 0x94 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID10 Message Buffer 10 ID Register CAN0 0x124 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID11 Message Buffer 11 ID Register CAN0 0x134 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID12 Message Buffer 12 ID Register CAN0 0x144 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID13 Message Buffer 13 ID Register CAN0 0x154 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID14 Message Buffer 14 ID Register CAN0 0x164 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID15 Message Buffer 15 ID Register CAN0 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID16 Message Buffer 16 ID Register CAN0 0x184 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID17 Message Buffer 17 ID Register CAN0 0x194 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID18 Message Buffer 18 ID Register CAN0 0x1A4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID19 Message Buffer 19 ID Register CAN0 0x1B4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID2 Message Buffer 2 ID Register CAN0 0xA4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID20 Message Buffer 20 ID Register CAN0 0x1C4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID21 Message Buffer 21 ID Register CAN0 0x1D4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID22 Message Buffer 22 ID Register CAN0 0x1E4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID23 Message Buffer 23 ID Register CAN0 0x1F4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID24 Message Buffer 24 ID Register CAN0 0x204 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID25 Message Buffer 25 ID Register CAN0 0x214 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID26 Message Buffer 26 ID Register CAN0 0x224 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID27 Message Buffer 27 ID Register CAN0 0x234 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID28 Message Buffer 28 ID Register CAN0 0x244 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID29 Message Buffer 29 ID Register CAN0 0x254 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID3 Message Buffer 3 ID Register CAN0 0xB4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID30 Message Buffer 30 ID Register CAN0 0x264 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID31 Message Buffer 31 ID Register CAN0 0x274 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID4 Message Buffer 4 ID Register CAN0 0xC4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID5 Message Buffer 5 ID Register CAN0 0xD4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID6 Message Buffer 6 ID Register CAN0 0xE4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID7 Message Buffer 7 ID Register CAN0 0xF4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID8 Message Buffer 8 ID Register CAN0 0x104 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID9 Message Buffer 9 ID Register CAN0 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write IFLAG1 Interrupt Flags 1 register 0x30 32 read-write n 0x0 0x0 BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write BUF4TO1I Buffer MB i Interrupt Or reserved 1 4 read-write BUF5I Buffer MB5 Interrupt Or Frames available in Rx FIFO 5 1 read-write 0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 #0 1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. #1 BUF6I Buffer MB6 Interrupt Or Rx FIFO Warning 6 1 read-write 0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 #0 1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 #1 BUF7I Buffer MB7 Interrupt Or Rx FIFO Overflow 7 1 read-write 0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 #0 1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 #1 IMASK1 Interrupt Masks 1 register 0x28 32 read-write n 0x0 0x0 BUF31TO0M Buffer MB i Mask 0 32 read-write MB0_16B_CS Message Buffer 0 CS Register CAN0 0x80 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB0_16B_ID Message Buffer 0 ID Register CAN0 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB0_16B_WORD0 Message Buffer 0 WORD_16B Register CAN0 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_16B_WORD1 Message Buffer 0 WORD_16B Register CAN0 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_16B_WORD2 Message Buffer 0 WORD_16B Register CAN0 0x90 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB0_16B_WORD3 Message Buffer 0 WORD_16B Register CAN0 0x94 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_32B_CS Message Buffer 0 CS Register CAN0 0x80 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB0_32B_ID Message Buffer 0 ID Register CAN0 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB0_32B_WORD0 Message Buffer 0 WORD_32B Register CAN0 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_32B_WORD1 Message Buffer 0 WORD_32B Register CAN0 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_32B_WORD2 Message Buffer 0 WORD_32B Register CAN0 0x90 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB0_32B_WORD3 Message Buffer 0 WORD_32B Register CAN0 0x94 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_32B_WORD4 Message Buffer 0 WORD_32B Register CAN0 0x98 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_32B_WORD5 Message Buffer 0 WORD_32B Register CAN0 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_32B_WORD6 Message Buffer 0 WORD_32B Register CAN0 0xA0 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_32B_WORD7 Message Buffer 0 WORD_32B Register CAN0 0xA4 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_CS Message Buffer 0 CS Register CAN0 0x80 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB0_64B_ID Message Buffer 0 ID Register CAN0 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB0_64B_WORD0 Message Buffer 0 WORD_64B Register CAN0 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD1 Message Buffer 0 WORD_64B Register CAN0 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD10 Message Buffer 0 WORD_64B Register CAN0 0xB0 32 read-write n 0x0 0x0 DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD11 Message Buffer 0 WORD_64B Register CAN0 0xB4 32 read-write n 0x0 0x0 DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD12 Message Buffer 0 WORD_64B Register CAN0 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD13 Message Buffer 0 WORD_64B Register CAN0 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD14 Message Buffer 0 WORD_64B Register CAN0 0xC0 32 read-write n 0x0 0x0 DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD15 Message Buffer 0 WORD_64B Register CAN0 0xC4 32 read-write n 0x0 0x0 DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD2 Message Buffer 0 WORD_64B Register CAN0 0x90 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB0_64B_WORD3 Message Buffer 0 WORD_64B Register CAN0 0x94 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD4 Message Buffer 0 WORD_64B Register CAN0 0x98 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD5 Message Buffer 0 WORD_64B Register CAN0 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD6 Message Buffer 0 WORD_64B Register CAN0 0xA0 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD7 Message Buffer 0 WORD_64B Register CAN0 0xA4 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD8 Message Buffer 0 WORD_64B Register CAN0 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_64B_WORD9 Message Buffer 0 WORD_64B Register CAN0 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_8B_CS Message Buffer 0 CS Register CAN0 0x80 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB0_8B_ID Message Buffer 0 ID Register CAN0 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB0_8B_WORD0 Message Buffer 0 WORD_8B Register CAN0 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB0_8B_WORD1 Message Buffer 0 WORD_8B Register CAN0 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_16B_CS Message Buffer 10 CS Register CAN0 0x170 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB10_16B_ID Message Buffer 10 ID Register CAN0 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB10_16B_WORD0 Message Buffer 10 WORD_16B Register CAN0 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_16B_WORD1 Message Buffer 10 WORD_16B Register CAN0 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_16B_WORD2 Message Buffer 10 WORD_16B Register CAN0 0x180 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB10_16B_WORD3 Message Buffer 10 WORD_16B Register CAN0 0x184 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_32B_CS Message Buffer 10 CS Register CAN0 0x210 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB10_32B_ID Message Buffer 10 ID Register CAN0 0x214 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB10_32B_WORD0 Message Buffer 10 WORD_32B Register CAN0 0x218 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_32B_WORD1 Message Buffer 10 WORD_32B Register CAN0 0x21C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_32B_WORD2 Message Buffer 10 WORD_32B Register CAN0 0x220 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB10_32B_WORD3 Message Buffer 10 WORD_32B Register CAN0 0x224 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_32B_WORD4 Message Buffer 10 WORD_32B Register CAN0 0x228 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_32B_WORD5 Message Buffer 10 WORD_32B Register CAN0 0x22C 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_32B_WORD6 Message Buffer 10 WORD_32B Register CAN0 0x230 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_32B_WORD7 Message Buffer 10 WORD_32B Register CAN0 0x234 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_8B_CS Message Buffer 10 CS Register CAN0 0x120 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB10_8B_ID Message Buffer 10 ID Register CAN0 0x124 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB10_8B_WORD0 Message Buffer 10 WORD_8B Register CAN0 0x128 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB10_8B_WORD1 Message Buffer 10 WORD_8B Register CAN0 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_16B_CS Message Buffer 11 CS Register CAN0 0x188 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB11_16B_ID Message Buffer 11 ID Register CAN0 0x18C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB11_16B_WORD0 Message Buffer 11 WORD_16B Register CAN0 0x190 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_16B_WORD1 Message Buffer 11 WORD_16B Register CAN0 0x194 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_16B_WORD2 Message Buffer 11 WORD_16B Register CAN0 0x198 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB11_16B_WORD3 Message Buffer 11 WORD_16B Register CAN0 0x19C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_32B_CS Message Buffer 11 CS Register CAN0 0x238 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB11_32B_ID Message Buffer 11 ID Register CAN0 0x23C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB11_32B_WORD0 Message Buffer 11 WORD_32B Register CAN0 0x240 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_32B_WORD1 Message Buffer 11 WORD_32B Register CAN0 0x244 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_32B_WORD2 Message Buffer 11 WORD_32B Register CAN0 0x248 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB11_32B_WORD3 Message Buffer 11 WORD_32B Register CAN0 0x24C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_32B_WORD4 Message Buffer 11 WORD_32B Register CAN0 0x250 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_32B_WORD5 Message Buffer 11 WORD_32B Register CAN0 0x254 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_32B_WORD6 Message Buffer 11 WORD_32B Register CAN0 0x258 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_32B_WORD7 Message Buffer 11 WORD_32B Register CAN0 0x25C 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_8B_CS Message Buffer 11 CS Register CAN0 0x130 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB11_8B_ID Message Buffer 11 ID Register CAN0 0x134 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB11_8B_WORD0 Message Buffer 11 WORD_8B Register CAN0 0x138 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB11_8B_WORD1 Message Buffer 11 WORD_8B Register CAN0 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB12_16B_CS Message Buffer 12 CS Register CAN0 0x1A0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB12_16B_ID Message Buffer 12 ID Register CAN0 0x1A4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB12_16B_WORD0 Message Buffer 12 WORD_16B Register CAN0 0x1A8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB12_16B_WORD1 Message Buffer 12 WORD_16B Register CAN0 0x1AC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB12_16B_WORD2 Message Buffer 12 WORD_16B Register CAN0 0x1B0 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB12_16B_WORD3 Message Buffer 12 WORD_16B Register CAN0 0x1B4 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB12_8B_CS Message Buffer 12 CS Register CAN0 0x140 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB12_8B_ID Message Buffer 12 ID Register CAN0 0x144 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB12_8B_WORD0 Message Buffer 12 WORD_8B Register CAN0 0x148 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB12_8B_WORD1 Message Buffer 12 WORD_8B Register CAN0 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB13_16B_CS Message Buffer 13 CS Register CAN0 0x1B8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB13_16B_ID Message Buffer 13 ID Register CAN0 0x1BC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB13_16B_WORD0 Message Buffer 13 WORD_16B Register CAN0 0x1C0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB13_16B_WORD1 Message Buffer 13 WORD_16B Register CAN0 0x1C4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB13_16B_WORD2 Message Buffer 13 WORD_16B Register CAN0 0x1C8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB13_16B_WORD3 Message Buffer 13 WORD_16B Register CAN0 0x1CC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB13_8B_CS Message Buffer 13 CS Register CAN0 0x150 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB13_8B_ID Message Buffer 13 ID Register CAN0 0x154 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB13_8B_WORD0 Message Buffer 13 WORD_8B Register CAN0 0x158 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB13_8B_WORD1 Message Buffer 13 WORD_8B Register CAN0 0x15C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB14_16B_CS Message Buffer 14 CS Register CAN0 0x1D0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB14_16B_ID Message Buffer 14 ID Register CAN0 0x1D4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB14_16B_WORD0 Message Buffer 14 WORD_16B Register CAN0 0x1D8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB14_16B_WORD1 Message Buffer 14 WORD_16B Register CAN0 0x1DC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB14_16B_WORD2 Message Buffer 14 WORD_16B Register CAN0 0x1E0 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB14_16B_WORD3 Message Buffer 14 WORD_16B Register CAN0 0x1E4 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB14_8B_CS Message Buffer 14 CS Register CAN0 0x160 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB14_8B_ID Message Buffer 14 ID Register CAN0 0x164 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB14_8B_WORD0 Message Buffer 14 WORD_8B Register CAN0 0x168 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB14_8B_WORD1 Message Buffer 14 WORD_8B Register CAN0 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB15_16B_CS Message Buffer 15 CS Register CAN0 0x1E8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB15_16B_ID Message Buffer 15 ID Register CAN0 0x1EC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB15_16B_WORD0 Message Buffer 15 WORD_16B Register CAN0 0x1F0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB15_16B_WORD1 Message Buffer 15 WORD_16B Register CAN0 0x1F4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB15_16B_WORD2 Message Buffer 15 WORD_16B Register CAN0 0x1F8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB15_16B_WORD3 Message Buffer 15 WORD_16B Register CAN0 0x1FC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB15_8B_CS Message Buffer 15 CS Register CAN0 0x170 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB15_8B_ID Message Buffer 15 ID Register CAN0 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB15_8B_WORD0 Message Buffer 15 WORD_8B Register CAN0 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB15_8B_WORD1 Message Buffer 15 WORD_8B Register CAN0 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB16_16B_CS Message Buffer 16 CS Register CAN0 0x200 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB16_16B_ID Message Buffer 16 ID Register CAN0 0x204 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB16_16B_WORD0 Message Buffer 16 WORD_16B Register CAN0 0x208 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB16_16B_WORD1 Message Buffer 16 WORD_16B Register CAN0 0x20C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB16_16B_WORD2 Message Buffer 16 WORD_16B Register CAN0 0x210 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB16_16B_WORD3 Message Buffer 16 WORD_16B Register CAN0 0x214 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB16_8B_CS Message Buffer 16 CS Register CAN0 0x180 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB16_8B_ID Message Buffer 16 ID Register CAN0 0x184 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB16_8B_WORD0 Message Buffer 16 WORD_8B Register CAN0 0x188 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB16_8B_WORD1 Message Buffer 16 WORD_8B Register CAN0 0x18C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB17_16B_CS Message Buffer 17 CS Register CAN0 0x218 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB17_16B_ID Message Buffer 17 ID Register CAN0 0x21C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB17_16B_WORD0 Message Buffer 17 WORD_16B Register CAN0 0x220 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB17_16B_WORD1 Message Buffer 17 WORD_16B Register CAN0 0x224 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB17_16B_WORD2 Message Buffer 17 WORD_16B Register CAN0 0x228 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB17_16B_WORD3 Message Buffer 17 WORD_16B Register CAN0 0x22C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB17_8B_CS Message Buffer 17 CS Register CAN0 0x190 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB17_8B_ID Message Buffer 17 ID Register CAN0 0x194 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB17_8B_WORD0 Message Buffer 17 WORD_8B Register CAN0 0x198 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB17_8B_WORD1 Message Buffer 17 WORD_8B Register CAN0 0x19C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB18_16B_CS Message Buffer 18 CS Register CAN0 0x230 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB18_16B_ID Message Buffer 18 ID Register CAN0 0x234 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB18_16B_WORD0 Message Buffer 18 WORD_16B Register CAN0 0x238 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB18_16B_WORD1 Message Buffer 18 WORD_16B Register CAN0 0x23C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB18_16B_WORD2 Message Buffer 18 WORD_16B Register CAN0 0x240 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB18_16B_WORD3 Message Buffer 18 WORD_16B Register CAN0 0x244 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB18_8B_CS Message Buffer 18 CS Register CAN0 0x1A0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB18_8B_ID Message Buffer 18 ID Register CAN0 0x1A4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB18_8B_WORD0 Message Buffer 18 WORD_8B Register CAN0 0x1A8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB18_8B_WORD1 Message Buffer 18 WORD_8B Register CAN0 0x1AC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB19_16B_CS Message Buffer 19 CS Register CAN0 0x248 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB19_16B_ID Message Buffer 19 ID Register CAN0 0x24C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB19_16B_WORD0 Message Buffer 19 WORD_16B Register CAN0 0x250 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB19_16B_WORD1 Message Buffer 19 WORD_16B Register CAN0 0x254 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB19_16B_WORD2 Message Buffer 19 WORD_16B Register CAN0 0x258 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB19_16B_WORD3 Message Buffer 19 WORD_16B Register CAN0 0x25C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB19_8B_CS Message Buffer 19 CS Register CAN0 0x1B0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB19_8B_ID Message Buffer 19 ID Register CAN0 0x1B4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB19_8B_WORD0 Message Buffer 19 WORD_8B Register CAN0 0x1B8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB19_8B_WORD1 Message Buffer 19 WORD_8B Register CAN0 0x1BC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_16B_CS Message Buffer 1 CS Register CAN0 0x98 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB1_16B_ID Message Buffer 1 ID Register CAN0 0x9C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB1_16B_WORD0 Message Buffer 1 WORD_16B Register CAN0 0xA0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_16B_WORD1 Message Buffer 1 WORD_16B Register CAN0 0xA4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_16B_WORD2 Message Buffer 1 WORD_16B Register CAN0 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB1_16B_WORD3 Message Buffer 1 WORD_16B Register CAN0 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_32B_CS Message Buffer 1 CS Register CAN0 0xA8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB1_32B_ID Message Buffer 1 ID Register CAN0 0xAC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB1_32B_WORD0 Message Buffer 1 WORD_32B Register CAN0 0xB0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_32B_WORD1 Message Buffer 1 WORD_32B Register CAN0 0xB4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_32B_WORD2 Message Buffer 1 WORD_32B Register CAN0 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB1_32B_WORD3 Message Buffer 1 WORD_32B Register CAN0 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_32B_WORD4 Message Buffer 1 WORD_32B Register CAN0 0xC0 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_32B_WORD5 Message Buffer 1 WORD_32B Register CAN0 0xC4 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_32B_WORD6 Message Buffer 1 WORD_32B Register CAN0 0xC8 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_32B_WORD7 Message Buffer 1 WORD_32B Register CAN0 0xCC 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_CS Message Buffer 1 CS Register CAN0 0xC8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB1_64B_ID Message Buffer 1 ID Register CAN0 0xCC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB1_64B_WORD0 Message Buffer 1 WORD_64B Register CAN0 0xD0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD1 Message Buffer 1 WORD_64B Register CAN0 0xD4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD10 Message Buffer 1 WORD_64B Register CAN0 0xF8 32 read-write n 0x0 0x0 DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD11 Message Buffer 1 WORD_64B Register CAN0 0xFC 32 read-write n 0x0 0x0 DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD12 Message Buffer 1 WORD_64B Register CAN0 0x100 32 read-write n 0x0 0x0 DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD13 Message Buffer 1 WORD_64B Register CAN0 0x104 32 read-write n 0x0 0x0 DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD14 Message Buffer 1 WORD_64B Register CAN0 0x108 32 read-write n 0x0 0x0 DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD15 Message Buffer 1 WORD_64B Register CAN0 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD2 Message Buffer 1 WORD_64B Register CAN0 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB1_64B_WORD3 Message Buffer 1 WORD_64B Register CAN0 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD4 Message Buffer 1 WORD_64B Register CAN0 0xE0 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD5 Message Buffer 1 WORD_64B Register CAN0 0xE4 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD6 Message Buffer 1 WORD_64B Register CAN0 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD7 Message Buffer 1 WORD_64B Register CAN0 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD8 Message Buffer 1 WORD_64B Register CAN0 0xF0 32 read-write n 0x0 0x0 DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_64B_WORD9 Message Buffer 1 WORD_64B Register CAN0 0xF4 32 read-write n 0x0 0x0 DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_8B_CS Message Buffer 1 CS Register CAN0 0x90 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB1_8B_ID Message Buffer 1 ID Register CAN0 0x94 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB1_8B_WORD0 Message Buffer 1 WORD_8B Register CAN0 0x98 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB1_8B_WORD1 Message Buffer 1 WORD_8B Register CAN0 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB20_16B_CS Message Buffer 20 CS Register CAN0 0x260 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB20_16B_ID Message Buffer 20 ID Register CAN0 0x264 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB20_16B_WORD0 Message Buffer 20 WORD_16B Register CAN0 0x268 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB20_16B_WORD1 Message Buffer 20 WORD_16B Register CAN0 0x26C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB20_16B_WORD2 Message Buffer 20 WORD_16B Register CAN0 0x270 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB20_16B_WORD3 Message Buffer 20 WORD_16B Register CAN0 0x274 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB20_8B_CS Message Buffer 20 CS Register CAN0 0x1C0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB20_8B_ID Message Buffer 20 ID Register CAN0 0x1C4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB20_8B_WORD0 Message Buffer 20 WORD_8B Register CAN0 0x1C8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB20_8B_WORD1 Message Buffer 20 WORD_8B Register CAN0 0x1CC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB21_8B_CS Message Buffer 21 CS Register CAN0 0x1D0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB21_8B_ID Message Buffer 21 ID Register CAN0 0x1D4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB21_8B_WORD0 Message Buffer 21 WORD_8B Register CAN0 0x1D8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB21_8B_WORD1 Message Buffer 21 WORD_8B Register CAN0 0x1DC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB22_8B_CS Message Buffer 22 CS Register CAN0 0x1E0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB22_8B_ID Message Buffer 22 ID Register CAN0 0x1E4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB22_8B_WORD0 Message Buffer 22 WORD_8B Register CAN0 0x1E8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB22_8B_WORD1 Message Buffer 22 WORD_8B Register CAN0 0x1EC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB23_8B_CS Message Buffer 23 CS Register CAN0 0x1F0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB23_8B_ID Message Buffer 23 ID Register CAN0 0x1F4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB23_8B_WORD0 Message Buffer 23 WORD_8B Register CAN0 0x1F8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB23_8B_WORD1 Message Buffer 23 WORD_8B Register CAN0 0x1FC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB24_8B_CS Message Buffer 24 CS Register CAN0 0x200 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB24_8B_ID Message Buffer 24 ID Register CAN0 0x204 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB24_8B_WORD0 Message Buffer 24 WORD_8B Register CAN0 0x208 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB24_8B_WORD1 Message Buffer 24 WORD_8B Register CAN0 0x20C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB25_8B_CS Message Buffer 25 CS Register CAN0 0x210 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB25_8B_ID Message Buffer 25 ID Register CAN0 0x214 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB25_8B_WORD0 Message Buffer 25 WORD_8B Register CAN0 0x218 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB25_8B_WORD1 Message Buffer 25 WORD_8B Register CAN0 0x21C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB26_8B_CS Message Buffer 26 CS Register CAN0 0x220 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB26_8B_ID Message Buffer 26 ID Register CAN0 0x224 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB26_8B_WORD0 Message Buffer 26 WORD_8B Register CAN0 0x228 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB26_8B_WORD1 Message Buffer 26 WORD_8B Register CAN0 0x22C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB27_8B_CS Message Buffer 27 CS Register CAN0 0x230 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB27_8B_ID Message Buffer 27 ID Register CAN0 0x234 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB27_8B_WORD0 Message Buffer 27 WORD_8B Register CAN0 0x238 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB27_8B_WORD1 Message Buffer 27 WORD_8B Register CAN0 0x23C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB28_8B_CS Message Buffer 28 CS Register CAN0 0x240 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB28_8B_ID Message Buffer 28 ID Register CAN0 0x244 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB28_8B_WORD0 Message Buffer 28 WORD_8B Register CAN0 0x248 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB28_8B_WORD1 Message Buffer 28 WORD_8B Register CAN0 0x24C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB29_8B_CS Message Buffer 29 CS Register CAN0 0x250 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB29_8B_ID Message Buffer 29 ID Register CAN0 0x254 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB29_8B_WORD0 Message Buffer 29 WORD_8B Register CAN0 0x258 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB29_8B_WORD1 Message Buffer 29 WORD_8B Register CAN0 0x25C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_16B_CS Message Buffer 2 CS Register CAN0 0xB0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB2_16B_ID Message Buffer 2 ID Register CAN0 0xB4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB2_16B_WORD0 Message Buffer 2 WORD_16B Register CAN0 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_16B_WORD1 Message Buffer 2 WORD_16B Register CAN0 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_16B_WORD2 Message Buffer 2 WORD_16B Register CAN0 0xC0 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB2_16B_WORD3 Message Buffer 2 WORD_16B Register CAN0 0xC4 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_32B_CS Message Buffer 2 CS Register CAN0 0xD0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB2_32B_ID Message Buffer 2 ID Register CAN0 0xD4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB2_32B_WORD0 Message Buffer 2 WORD_32B Register CAN0 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_32B_WORD1 Message Buffer 2 WORD_32B Register CAN0 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_32B_WORD2 Message Buffer 2 WORD_32B Register CAN0 0xE0 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB2_32B_WORD3 Message Buffer 2 WORD_32B Register CAN0 0xE4 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_32B_WORD4 Message Buffer 2 WORD_32B Register CAN0 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_32B_WORD5 Message Buffer 2 WORD_32B Register CAN0 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_32B_WORD6 Message Buffer 2 WORD_32B Register CAN0 0xF0 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_32B_WORD7 Message Buffer 2 WORD_32B Register CAN0 0xF4 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_CS Message Buffer 2 CS Register CAN0 0x110 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB2_64B_ID Message Buffer 2 ID Register CAN0 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB2_64B_WORD0 Message Buffer 2 WORD_64B Register CAN0 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD1 Message Buffer 2 WORD_64B Register CAN0 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD10 Message Buffer 2 WORD_64B Register CAN0 0x140 32 read-write n 0x0 0x0 DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD11 Message Buffer 2 WORD_64B Register CAN0 0x144 32 read-write n 0x0 0x0 DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD12 Message Buffer 2 WORD_64B Register CAN0 0x148 32 read-write n 0x0 0x0 DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD13 Message Buffer 2 WORD_64B Register CAN0 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD14 Message Buffer 2 WORD_64B Register CAN0 0x150 32 read-write n 0x0 0x0 DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD15 Message Buffer 2 WORD_64B Register CAN0 0x154 32 read-write n 0x0 0x0 DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD2 Message Buffer 2 WORD_64B Register CAN0 0x120 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB2_64B_WORD3 Message Buffer 2 WORD_64B Register CAN0 0x124 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD4 Message Buffer 2 WORD_64B Register CAN0 0x128 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD5 Message Buffer 2 WORD_64B Register CAN0 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD6 Message Buffer 2 WORD_64B Register CAN0 0x130 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD7 Message Buffer 2 WORD_64B Register CAN0 0x134 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD8 Message Buffer 2 WORD_64B Register CAN0 0x138 32 read-write n 0x0 0x0 DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_64B_WORD9 Message Buffer 2 WORD_64B Register CAN0 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_8B_CS Message Buffer 2 CS Register CAN0 0xA0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB2_8B_ID Message Buffer 2 ID Register CAN0 0xA4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB2_8B_WORD0 Message Buffer 2 WORD_8B Register CAN0 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB2_8B_WORD1 Message Buffer 2 WORD_8B Register CAN0 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB30_8B_CS Message Buffer 30 CS Register CAN0 0x260 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB30_8B_ID Message Buffer 30 ID Register CAN0 0x264 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB30_8B_WORD0 Message Buffer 30 WORD_8B Register CAN0 0x268 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB30_8B_WORD1 Message Buffer 30 WORD_8B Register CAN0 0x26C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB31_8B_CS Message Buffer 31 CS Register CAN0 0x270 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB31_8B_ID Message Buffer 31 ID Register CAN0 0x274 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB31_8B_WORD0 Message Buffer 31 WORD_8B Register CAN0 0x278 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB31_8B_WORD1 Message Buffer 31 WORD_8B Register CAN0 0x27C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_16B_CS Message Buffer 3 CS Register CAN0 0xC8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB3_16B_ID Message Buffer 3 ID Register CAN0 0xCC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB3_16B_WORD0 Message Buffer 3 WORD_16B Register CAN0 0xD0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_16B_WORD1 Message Buffer 3 WORD_16B Register CAN0 0xD4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_16B_WORD2 Message Buffer 3 WORD_16B Register CAN0 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB3_16B_WORD3 Message Buffer 3 WORD_16B Register CAN0 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_32B_CS Message Buffer 3 CS Register CAN0 0xF8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB3_32B_ID Message Buffer 3 ID Register CAN0 0xFC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB3_32B_WORD0 Message Buffer 3 WORD_32B Register CAN0 0x100 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_32B_WORD1 Message Buffer 3 WORD_32B Register CAN0 0x104 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_32B_WORD2 Message Buffer 3 WORD_32B Register CAN0 0x108 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB3_32B_WORD3 Message Buffer 3 WORD_32B Register CAN0 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_32B_WORD4 Message Buffer 3 WORD_32B Register CAN0 0x110 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_32B_WORD5 Message Buffer 3 WORD_32B Register CAN0 0x114 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_32B_WORD6 Message Buffer 3 WORD_32B Register CAN0 0x118 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_32B_WORD7 Message Buffer 3 WORD_32B Register CAN0 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_CS Message Buffer 3 CS Register CAN0 0x158 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB3_64B_ID Message Buffer 3 ID Register CAN0 0x15C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB3_64B_WORD0 Message Buffer 3 WORD_64B Register CAN0 0x160 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD1 Message Buffer 3 WORD_64B Register CAN0 0x164 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD10 Message Buffer 3 WORD_64B Register CAN0 0x188 32 read-write n 0x0 0x0 DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD11 Message Buffer 3 WORD_64B Register CAN0 0x18C 32 read-write n 0x0 0x0 DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD12 Message Buffer 3 WORD_64B Register CAN0 0x190 32 read-write n 0x0 0x0 DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD13 Message Buffer 3 WORD_64B Register CAN0 0x194 32 read-write n 0x0 0x0 DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD14 Message Buffer 3 WORD_64B Register CAN0 0x198 32 read-write n 0x0 0x0 DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD15 Message Buffer 3 WORD_64B Register CAN0 0x19C 32 read-write n 0x0 0x0 DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD2 Message Buffer 3 WORD_64B Register CAN0 0x168 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB3_64B_WORD3 Message Buffer 3 WORD_64B Register CAN0 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD4 Message Buffer 3 WORD_64B Register CAN0 0x170 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD5 Message Buffer 3 WORD_64B Register CAN0 0x174 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD6 Message Buffer 3 WORD_64B Register CAN0 0x178 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD7 Message Buffer 3 WORD_64B Register CAN0 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD8 Message Buffer 3 WORD_64B Register CAN0 0x180 32 read-write n 0x0 0x0 DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_64B_WORD9 Message Buffer 3 WORD_64B Register CAN0 0x184 32 read-write n 0x0 0x0 DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_8B_CS Message Buffer 3 CS Register CAN0 0xB0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB3_8B_ID Message Buffer 3 ID Register CAN0 0xB4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB3_8B_WORD0 Message Buffer 3 WORD_8B Register CAN0 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB3_8B_WORD1 Message Buffer 3 WORD_8B Register CAN0 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_16B_CS Message Buffer 4 CS Register CAN0 0xE0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB4_16B_ID Message Buffer 4 ID Register CAN0 0xE4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB4_16B_WORD0 Message Buffer 4 WORD_16B Register CAN0 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_16B_WORD1 Message Buffer 4 WORD_16B Register CAN0 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_16B_WORD2 Message Buffer 4 WORD_16B Register CAN0 0xF0 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB4_16B_WORD3 Message Buffer 4 WORD_16B Register CAN0 0xF4 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_32B_CS Message Buffer 4 CS Register CAN0 0x120 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB4_32B_ID Message Buffer 4 ID Register CAN0 0x124 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB4_32B_WORD0 Message Buffer 4 WORD_32B Register CAN0 0x128 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_32B_WORD1 Message Buffer 4 WORD_32B Register CAN0 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_32B_WORD2 Message Buffer 4 WORD_32B Register CAN0 0x130 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB4_32B_WORD3 Message Buffer 4 WORD_32B Register CAN0 0x134 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_32B_WORD4 Message Buffer 4 WORD_32B Register CAN0 0x138 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_32B_WORD5 Message Buffer 4 WORD_32B Register CAN0 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_32B_WORD6 Message Buffer 4 WORD_32B Register CAN0 0x140 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_32B_WORD7 Message Buffer 4 WORD_32B Register CAN0 0x144 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_CS Message Buffer 4 CS Register CAN0 0x1A0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB4_64B_ID Message Buffer 4 ID Register CAN0 0x1A4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB4_64B_WORD0 Message Buffer 4 WORD_64B Register CAN0 0x1A8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD1 Message Buffer 4 WORD_64B Register CAN0 0x1AC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD10 Message Buffer 4 WORD_64B Register CAN0 0x1D0 32 read-write n 0x0 0x0 DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD11 Message Buffer 4 WORD_64B Register CAN0 0x1D4 32 read-write n 0x0 0x0 DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD12 Message Buffer 4 WORD_64B Register CAN0 0x1D8 32 read-write n 0x0 0x0 DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD13 Message Buffer 4 WORD_64B Register CAN0 0x1DC 32 read-write n 0x0 0x0 DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD14 Message Buffer 4 WORD_64B Register CAN0 0x1E0 32 read-write n 0x0 0x0 DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD15 Message Buffer 4 WORD_64B Register CAN0 0x1E4 32 read-write n 0x0 0x0 DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD2 Message Buffer 4 WORD_64B Register CAN0 0x1B0 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB4_64B_WORD3 Message Buffer 4 WORD_64B Register CAN0 0x1B4 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD4 Message Buffer 4 WORD_64B Register CAN0 0x1B8 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD5 Message Buffer 4 WORD_64B Register CAN0 0x1BC 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD6 Message Buffer 4 WORD_64B Register CAN0 0x1C0 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD7 Message Buffer 4 WORD_64B Register CAN0 0x1C4 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD8 Message Buffer 4 WORD_64B Register CAN0 0x1C8 32 read-write n 0x0 0x0 DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_64B_WORD9 Message Buffer 4 WORD_64B Register CAN0 0x1CC 32 read-write n 0x0 0x0 DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_8B_CS Message Buffer 4 CS Register CAN0 0xC0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB4_8B_ID Message Buffer 4 ID Register CAN0 0xC4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB4_8B_WORD0 Message Buffer 4 WORD_8B Register CAN0 0xC8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB4_8B_WORD1 Message Buffer 4 WORD_8B Register CAN0 0xCC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_16B_CS Message Buffer 5 CS Register CAN0 0xF8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB5_16B_ID Message Buffer 5 ID Register CAN0 0xFC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB5_16B_WORD0 Message Buffer 5 WORD_16B Register CAN0 0x100 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_16B_WORD1 Message Buffer 5 WORD_16B Register CAN0 0x104 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_16B_WORD2 Message Buffer 5 WORD_16B Register CAN0 0x108 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB5_16B_WORD3 Message Buffer 5 WORD_16B Register CAN0 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_32B_CS Message Buffer 5 CS Register CAN0 0x148 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB5_32B_ID Message Buffer 5 ID Register CAN0 0x14C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB5_32B_WORD0 Message Buffer 5 WORD_32B Register CAN0 0x150 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_32B_WORD1 Message Buffer 5 WORD_32B Register CAN0 0x154 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_32B_WORD2 Message Buffer 5 WORD_32B Register CAN0 0x158 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB5_32B_WORD3 Message Buffer 5 WORD_32B Register CAN0 0x15C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_32B_WORD4 Message Buffer 5 WORD_32B Register CAN0 0x160 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_32B_WORD5 Message Buffer 5 WORD_32B Register CAN0 0x164 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_32B_WORD6 Message Buffer 5 WORD_32B Register CAN0 0x168 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_32B_WORD7 Message Buffer 5 WORD_32B Register CAN0 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_CS Message Buffer 5 CS Register CAN0 0x1E8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB5_64B_ID Message Buffer 5 ID Register CAN0 0x1EC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB5_64B_WORD0 Message Buffer 5 WORD_64B Register CAN0 0x1F0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD1 Message Buffer 5 WORD_64B Register CAN0 0x1F4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD10 Message Buffer 5 WORD_64B Register CAN0 0x218 32 read-write n 0x0 0x0 DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD11 Message Buffer 5 WORD_64B Register CAN0 0x21C 32 read-write n 0x0 0x0 DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD12 Message Buffer 5 WORD_64B Register CAN0 0x220 32 read-write n 0x0 0x0 DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD13 Message Buffer 5 WORD_64B Register CAN0 0x224 32 read-write n 0x0 0x0 DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD14 Message Buffer 5 WORD_64B Register CAN0 0x228 32 read-write n 0x0 0x0 DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD15 Message Buffer 5 WORD_64B Register CAN0 0x22C 32 read-write n 0x0 0x0 DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD2 Message Buffer 5 WORD_64B Register CAN0 0x1F8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB5_64B_WORD3 Message Buffer 5 WORD_64B Register CAN0 0x1FC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD4 Message Buffer 5 WORD_64B Register CAN0 0x200 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD5 Message Buffer 5 WORD_64B Register CAN0 0x204 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD6 Message Buffer 5 WORD_64B Register CAN0 0x208 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD7 Message Buffer 5 WORD_64B Register CAN0 0x20C 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD8 Message Buffer 5 WORD_64B Register CAN0 0x210 32 read-write n 0x0 0x0 DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_64B_WORD9 Message Buffer 5 WORD_64B Register CAN0 0x214 32 read-write n 0x0 0x0 DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_8B_CS Message Buffer 5 CS Register CAN0 0xD0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB5_8B_ID Message Buffer 5 ID Register CAN0 0xD4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB5_8B_WORD0 Message Buffer 5 WORD_8B Register CAN0 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB5_8B_WORD1 Message Buffer 5 WORD_8B Register CAN0 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_16B_CS Message Buffer 6 CS Register CAN0 0x110 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB6_16B_ID Message Buffer 6 ID Register CAN0 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB6_16B_WORD0 Message Buffer 6 WORD_16B Register CAN0 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_16B_WORD1 Message Buffer 6 WORD_16B Register CAN0 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_16B_WORD2 Message Buffer 6 WORD_16B Register CAN0 0x120 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB6_16B_WORD3 Message Buffer 6 WORD_16B Register CAN0 0x124 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_32B_CS Message Buffer 6 CS Register CAN0 0x170 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB6_32B_ID Message Buffer 6 ID Register CAN0 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB6_32B_WORD0 Message Buffer 6 WORD_32B Register CAN0 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_32B_WORD1 Message Buffer 6 WORD_32B Register CAN0 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_32B_WORD2 Message Buffer 6 WORD_32B Register CAN0 0x180 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB6_32B_WORD3 Message Buffer 6 WORD_32B Register CAN0 0x184 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_32B_WORD4 Message Buffer 6 WORD_32B Register CAN0 0x188 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_32B_WORD5 Message Buffer 6 WORD_32B Register CAN0 0x18C 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_32B_WORD6 Message Buffer 6 WORD_32B Register CAN0 0x190 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_32B_WORD7 Message Buffer 6 WORD_32B Register CAN0 0x194 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_CS Message Buffer 6 CS Register CAN0 0x230 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB6_64B_ID Message Buffer 6 ID Register CAN0 0x234 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB6_64B_WORD0 Message Buffer 6 WORD_64B Register CAN0 0x238 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD1 Message Buffer 6 WORD_64B Register CAN0 0x23C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD10 Message Buffer 6 WORD_64B Register CAN0 0x260 32 read-write n 0x0 0x0 DATA_BYTE_40 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_41 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_42 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_43 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD11 Message Buffer 6 WORD_64B Register CAN0 0x264 32 read-write n 0x0 0x0 DATA_BYTE_44 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_45 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_46 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_47 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD12 Message Buffer 6 WORD_64B Register CAN0 0x268 32 read-write n 0x0 0x0 DATA_BYTE_48 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_49 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_50 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_51 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD13 Message Buffer 6 WORD_64B Register CAN0 0x26C 32 read-write n 0x0 0x0 DATA_BYTE_52 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_53 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_54 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_55 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD14 Message Buffer 6 WORD_64B Register CAN0 0x270 32 read-write n 0x0 0x0 DATA_BYTE_56 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_57 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_58 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_59 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD15 Message Buffer 6 WORD_64B Register CAN0 0x274 32 read-write n 0x0 0x0 DATA_BYTE_60 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_61 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_62 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_63 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD2 Message Buffer 6 WORD_64B Register CAN0 0x240 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB6_64B_WORD3 Message Buffer 6 WORD_64B Register CAN0 0x244 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD4 Message Buffer 6 WORD_64B Register CAN0 0x248 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD5 Message Buffer 6 WORD_64B Register CAN0 0x24C 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD6 Message Buffer 6 WORD_64B Register CAN0 0x250 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD7 Message Buffer 6 WORD_64B Register CAN0 0x254 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD8 Message Buffer 6 WORD_64B Register CAN0 0x258 32 read-write n 0x0 0x0 DATA_BYTE_32 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_33 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_34 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_35 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_64B_WORD9 Message Buffer 6 WORD_64B Register CAN0 0x25C 32 read-write n 0x0 0x0 DATA_BYTE_36 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_37 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_38 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_39 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_8B_CS Message Buffer 6 CS Register CAN0 0xE0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB6_8B_ID Message Buffer 6 ID Register CAN0 0xE4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB6_8B_WORD0 Message Buffer 6 WORD_8B Register CAN0 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB6_8B_WORD1 Message Buffer 6 WORD_8B Register CAN0 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_16B_CS Message Buffer 7 CS Register CAN0 0x128 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB7_16B_ID Message Buffer 7 ID Register CAN0 0x12C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB7_16B_WORD0 Message Buffer 7 WORD_16B Register CAN0 0x130 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_16B_WORD1 Message Buffer 7 WORD_16B Register CAN0 0x134 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_16B_WORD2 Message Buffer 7 WORD_16B Register CAN0 0x138 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB7_16B_WORD3 Message Buffer 7 WORD_16B Register CAN0 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_32B_CS Message Buffer 7 CS Register CAN0 0x198 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB7_32B_ID Message Buffer 7 ID Register CAN0 0x19C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB7_32B_WORD0 Message Buffer 7 WORD_32B Register CAN0 0x1A0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_32B_WORD1 Message Buffer 7 WORD_32B Register CAN0 0x1A4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_32B_WORD2 Message Buffer 7 WORD_32B Register CAN0 0x1A8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB7_32B_WORD3 Message Buffer 7 WORD_32B Register CAN0 0x1AC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_32B_WORD4 Message Buffer 7 WORD_32B Register CAN0 0x1B0 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_32B_WORD5 Message Buffer 7 WORD_32B Register CAN0 0x1B4 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_32B_WORD6 Message Buffer 7 WORD_32B Register CAN0 0x1B8 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_32B_WORD7 Message Buffer 7 WORD_32B Register CAN0 0x1BC 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_8B_CS Message Buffer 7 CS Register CAN0 0xF0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB7_8B_ID Message Buffer 7 ID Register CAN0 0xF4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB7_8B_WORD0 Message Buffer 7 WORD_8B Register CAN0 0xF8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB7_8B_WORD1 Message Buffer 7 WORD_8B Register CAN0 0xFC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_16B_CS Message Buffer 8 CS Register CAN0 0x140 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB8_16B_ID Message Buffer 8 ID Register CAN0 0x144 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB8_16B_WORD0 Message Buffer 8 WORD_16B Register CAN0 0x148 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_16B_WORD1 Message Buffer 8 WORD_16B Register CAN0 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_16B_WORD2 Message Buffer 8 WORD_16B Register CAN0 0x150 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB8_16B_WORD3 Message Buffer 8 WORD_16B Register CAN0 0x154 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_32B_CS Message Buffer 8 CS Register CAN0 0x1C0 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB8_32B_ID Message Buffer 8 ID Register CAN0 0x1C4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB8_32B_WORD0 Message Buffer 8 WORD_32B Register CAN0 0x1C8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_32B_WORD1 Message Buffer 8 WORD_32B Register CAN0 0x1CC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_32B_WORD2 Message Buffer 8 WORD_32B Register CAN0 0x1D0 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB8_32B_WORD3 Message Buffer 8 WORD_32B Register CAN0 0x1D4 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_32B_WORD4 Message Buffer 8 WORD_32B Register CAN0 0x1D8 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_32B_WORD5 Message Buffer 8 WORD_32B Register CAN0 0x1DC 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_32B_WORD6 Message Buffer 8 WORD_32B Register CAN0 0x1E0 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_32B_WORD7 Message Buffer 8 WORD_32B Register CAN0 0x1E4 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_8B_CS Message Buffer 8 CS Register CAN0 0x100 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB8_8B_ID Message Buffer 8 ID Register CAN0 0x104 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB8_8B_WORD0 Message Buffer 8 WORD_8B Register CAN0 0x108 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB8_8B_WORD1 Message Buffer 8 WORD_8B Register CAN0 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_16B_CS Message Buffer 9 CS Register CAN0 0x158 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB9_16B_ID Message Buffer 9 ID Register CAN0 0x15C 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB9_16B_WORD0 Message Buffer 9 WORD_16B Register CAN0 0x160 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_16B_WORD1 Message Buffer 9 WORD_16B Register CAN0 0x164 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_16B_WORD2 Message Buffer 9 WORD_16B Register CAN0 0x168 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB9_16B_WORD3 Message Buffer 9 WORD_16B Register CAN0 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_32B_CS Message Buffer 9 CS Register CAN0 0x1E8 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB9_32B_ID Message Buffer 9 ID Register CAN0 0x1EC 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB9_32B_WORD0 Message Buffer 9 WORD_32B Register CAN0 0x1F0 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_32B_WORD1 Message Buffer 9 WORD_32B Register CAN0 0x1F4 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_32B_WORD2 Message Buffer 9 WORD_32B Register CAN0 0x1F8 32 read-write n 0x0 0x0 DATA_BYTE_10 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_11 Data byte 0 of Rx/Tx frame. 0 8 read-write DATA_BYTE_8 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_9 Data byte 2 of Rx/Tx frame. 16 8 read-write MB9_32B_WORD3 Message Buffer 9 WORD_32B Register CAN0 0x1FC 32 read-write n 0x0 0x0 DATA_BYTE_12 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_13 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_14 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_15 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_32B_WORD4 Message Buffer 9 WORD_32B Register CAN0 0x200 32 read-write n 0x0 0x0 DATA_BYTE_16 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_17 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_18 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_19 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_32B_WORD5 Message Buffer 9 WORD_32B Register CAN0 0x204 32 read-write n 0x0 0x0 DATA_BYTE_20 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_21 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_22 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_23 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_32B_WORD6 Message Buffer 9 WORD_32B Register CAN0 0x208 32 read-write n 0x0 0x0 DATA_BYTE_24 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_25 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_26 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_27 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_32B_WORD7 Message Buffer 9 WORD_32B Register CAN0 0x20C 32 read-write n 0x0 0x0 DATA_BYTE_28 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_29 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_30 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_31 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_8B_CS Message Buffer 9 CS Register CAN0 0x110 32 read-write n 0x0 0x0 BRS Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. 30 1 read-write CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. 31 1 read-write ESI Error State Indicator. This bit indicates if the transmitting node is error active or error passive. 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write MB9_8B_ID Message Buffer 9 ID Register CAN0 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write MB9_8B_WORD0 Message Buffer 9 WORD_8B Register CAN0 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write MB9_8B_WORD1 Message Buffer 9 WORD_8B Register CAN0 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 AEN Abort Enable 12 1 read-write 0 Abort disabled. #0 1 Abort enabled. #1 DMA DMA Enable 15 1 read-write 0 DMA feature for RX FIFO disabled. #0 1 DMA feature for RX FIFO enabled. #1 DOZE Doze Mode Enable 18 1 read-write 0 FlexCAN is not enabled to enter low-power mode when Doze mode is requested. #0 1 FlexCAN is enabled to enter low-power mode when Doze mode is requested. #1 FDEN CAN FD operation enable 11 1 read-write 0 CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. #0 1 CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze mode. #0 1 Enabled to enter Freeze mode. #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze mode, prescaler running. #0 1 FlexCAN in Freeze mode, prescaler stopped. #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze mode request. #0 1 Enters Freeze mode if the FRZ bit is asserted. #1 IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 LPMACK Low-Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low-power mode. #0 1 FlexCAN is in a low-power mode. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled. #0 1 Local Priority enabled. #1 MAXMB Number Of The Last Message Buffer 0 7 read-write MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. #0 RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled. #0 1 Rx FIFO enabled. #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request. #0 1 Resets the registers affected by soft reset. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled. #0 1 Self reception disabled. #1 SUPV Supervisor Mode 23 1 read-write WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 WAKSRC Wake Up Source 19 1 read-write 0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. #0 1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 RX14MASK Rx 14 Mask register 0x14 32 read-write n 0x0 0x0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write RX15MASK Rx 15 Mask register 0x18 32 read-write n 0x0 0x0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write n 0x0 0x0 FGM Rx FIFO Global Mask Bits 0 32 read-write RXFIR Rx FIFO Information Register 0x4C 32 read-only n 0x0 0x0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only RXIMR0 Rx Individual Mask Registers 0x880 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR1 Rx Individual Mask Registers 0x884 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR10 Rx Individual Mask Registers 0x8A8 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR11 Rx Individual Mask Registers 0x8AC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR12 Rx Individual Mask Registers 0x8B0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR13 Rx Individual Mask Registers 0x8B4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR14 Rx Individual Mask Registers 0x8B8 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR15 Rx Individual Mask Registers 0x8BC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR16 Rx Individual Mask Registers 0x8C0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR17 Rx Individual Mask Registers 0x8C4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR18 Rx Individual Mask Registers 0x8C8 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR19 Rx Individual Mask Registers 0x8CC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR2 Rx Individual Mask Registers 0x888 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR20 Rx Individual Mask Registers 0x8D0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR21 Rx Individual Mask Registers 0x8D4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR22 Rx Individual Mask Registers 0x8D8 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR23 Rx Individual Mask Registers 0x8DC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR24 Rx Individual Mask Registers 0x8E0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR25 Rx Individual Mask Registers 0x8E4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR26 Rx Individual Mask Registers 0x8E8 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR27 Rx Individual Mask Registers 0x8EC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR28 Rx Individual Mask Registers 0x8F0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR29 Rx Individual Mask Registers 0x8F4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR3 Rx Individual Mask Registers 0x88C 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR30 Rx Individual Mask Registers 0x8F8 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR31 Rx Individual Mask Registers 0x8FC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR4 Rx Individual Mask Registers 0x890 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR5 Rx Individual Mask Registers 0x894 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR6 Rx Individual Mask Registers 0x898 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR7 Rx Individual Mask Registers 0x89C 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR8 Rx Individual Mask Registers 0x8A0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXIMR9 Rx Individual Mask Registers 0x8A4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write n 0x0 0x0 MG Rx Mailboxes Global Mask Bits 0 32 read-write TIMER Free Running Timer 0x8 32 read-write n 0x0 0x0 TIMER Timer Value 0 16 read-write WORD00 Message Buffer 0 WORD0 Register CAN0 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD01 Message Buffer 1 WORD0 Register CAN0 0x98 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD010 Message Buffer 10 WORD0 Register CAN0 0x128 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD011 Message Buffer 11 WORD0 Register CAN0 0x138 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD012 Message Buffer 12 WORD0 Register CAN0 0x148 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD013 Message Buffer 13 WORD0 Register CAN0 0x158 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD014 Message Buffer 14 WORD0 Register CAN0 0x168 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD015 Message Buffer 15 WORD0 Register CAN0 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD016 Message Buffer 16 WORD0 Register CAN0 0x188 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD017 Message Buffer 17 WORD0 Register CAN0 0x198 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD018 Message Buffer 18 WORD0 Register CAN0 0x1A8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD019 Message Buffer 19 WORD0 Register CAN0 0x1B8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD02 Message Buffer 2 WORD0 Register CAN0 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD020 Message Buffer 20 WORD0 Register CAN0 0x1C8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD021 Message Buffer 21 WORD0 Register CAN0 0x1D8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD022 Message Buffer 22 WORD0 Register CAN0 0x1E8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD023 Message Buffer 23 WORD0 Register CAN0 0x1F8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD024 Message Buffer 24 WORD0 Register CAN0 0x208 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD025 Message Buffer 25 WORD0 Register CAN0 0x218 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD026 Message Buffer 26 WORD0 Register CAN0 0x228 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD027 Message Buffer 27 WORD0 Register CAN0 0x238 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD028 Message Buffer 28 WORD0 Register CAN0 0x248 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD029 Message Buffer 29 WORD0 Register CAN0 0x258 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD03 Message Buffer 3 WORD0 Register CAN0 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD030 Message Buffer 30 WORD0 Register CAN0 0x268 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD031 Message Buffer 31 WORD0 Register CAN0 0x278 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD04 Message Buffer 4 WORD0 Register CAN0 0xC8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD05 Message Buffer 5 WORD0 Register CAN0 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD06 Message Buffer 6 WORD0 Register CAN0 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD07 Message Buffer 7 WORD0 Register CAN0 0xF8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD08 Message Buffer 8 WORD0 Register CAN0 0x108 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD09 Message Buffer 9 WORD0 Register CAN0 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD10 Message Buffer 0 WORD1 Register CAN0 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD11 Message Buffer 1 WORD1 Register CAN0 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD110 Message Buffer 10 WORD1 Register CAN0 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD111 Message Buffer 11 WORD1 Register CAN0 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD112 Message Buffer 12 WORD1 Register CAN0 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD113 Message Buffer 13 WORD1 Register CAN0 0x15C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD114 Message Buffer 14 WORD1 Register CAN0 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD115 Message Buffer 15 WORD1 Register CAN0 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD116 Message Buffer 16 WORD1 Register CAN0 0x18C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD117 Message Buffer 17 WORD1 Register CAN0 0x19C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD118 Message Buffer 18 WORD1 Register CAN0 0x1AC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD119 Message Buffer 19 WORD1 Register CAN0 0x1BC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD12 Message Buffer 2 WORD1 Register CAN0 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD120 Message Buffer 20 WORD1 Register CAN0 0x1CC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD121 Message Buffer 21 WORD1 Register CAN0 0x1DC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD122 Message Buffer 22 WORD1 Register CAN0 0x1EC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD123 Message Buffer 23 WORD1 Register CAN0 0x1FC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD124 Message Buffer 24 WORD1 Register CAN0 0x20C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD125 Message Buffer 25 WORD1 Register CAN0 0x21C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD126 Message Buffer 26 WORD1 Register CAN0 0x22C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD127 Message Buffer 27 WORD1 Register CAN0 0x23C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD128 Message Buffer 28 WORD1 Register CAN0 0x24C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD129 Message Buffer 29 WORD1 Register CAN0 0x25C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD13 Message Buffer 3 WORD1 Register CAN0 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD130 Message Buffer 30 WORD1 Register CAN0 0x26C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD131 Message Buffer 31 WORD1 Register CAN0 0x27C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD14 Message Buffer 4 WORD1 Register CAN0 0xCC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD15 Message Buffer 5 WORD1 Register CAN0 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD16 Message Buffer 6 WORD1 Register CAN0 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD17 Message Buffer 7 WORD1 Register CAN0 0xFC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD18 Message Buffer 8 WORD1 Register CAN0 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write WORD19 Message Buffer 9 WORD1 Register CAN0 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 3 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 2 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 1 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 0 of Rx/Tx frame. 0 8 read-write CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP0 0x0 0x0 0x6 registers n CMP0 16 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSTM Pass Through Mode Enable 7 1 read-write 0 Pass Through Mode is disabled. #0 1 Pass Through Mode is enabled. #1 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CMT Carrier Modulator Transmitter CMT 0x0 0x0 0xC registers n CMT 14 CGH1 CMT Carrier Generator High Data Register 1 0x0 8 read-write n 0x0 0x0 PH Primary Carrier High Time Data Value 0 8 read-write CGH2 CMT Carrier Generator High Data Register 2 0x2 8 read-write n 0x0 0x0 SH Secondary Carrier High Time Data Value 0 8 read-write CGL1 CMT Carrier Generator Low Data Register 1 0x1 8 read-write n 0x0 0x0 PL Primary Carrier Low Time Data Value 0 8 read-write CGL2 CMT Carrier Generator Low Data Register 2 0x3 8 read-write n 0x0 0x0 SL Secondary Carrier Low Time Data Value 0 8 read-write CMD1 CMT Modulator Data Register Mark High 0x6 8 read-write n 0x0 0x0 MB MB[15:8] 0 8 read-write CMD2 CMT Modulator Data Register Mark Low 0x7 8 read-write n 0x0 0x0 MB MB[7:0] 0 8 read-write CMD3 CMT Modulator Data Register Space High 0x8 8 read-write n 0x0 0x0 SB SB[15:8] 0 8 read-write CMD4 CMT Modulator Data Register Space Low 0x9 8 read-write n 0x0 0x0 SB SB[7:0] 0 8 read-write DMA CMT Direct Memory Access Register 0xB 8 read-write n 0x0 0x0 DMA DMA Enable 0 1 read-write 0 DMA transfer request and done are disabled. #0 1 DMA transfer request and done are enabled. #1 MSC CMT Modulator Status and Control Register 0x5 8 read-write n 0x0 0x0 BASE Baseband Enable 3 1 read-write 0 Baseband mode is disabled. #0 1 Baseband mode is enabled. #1 CMTDIV CMT Clock Divide Prescaler 5 2 read-write 00 IF * 1 #00 01 IF * 2 #01 10 IF * 4 #10 11 IF * 8 #11 EOCF End Of Cycle Status Flag 7 1 read-only 0 End of modulation cycle has not occured since the flag last cleared. #0 1 End of modulator cycle has occurred. #1 EOCIE End of Cycle Interrupt Enable 1 1 read-write 0 CPU interrupt is disabled. #0 1 CPU interrupt is enabled. #1 EXSPC Extended Space Enable 4 1 read-write 0 Extended space is disabled. #0 1 Extended space is enabled. #1 FSK FSK Mode Select 2 1 read-write 0 The CMT operates in Time or Baseband mode. #0 1 The CMT operates in FSK mode. #1 MCGEN Modulator and Carrier Generator Enable 0 1 read-write 0 Modulator and carrier generator disabled #0 1 Modulator and carrier generator enabled #1 OC CMT Output Control Register 0x4 8 read-write n 0x0 0x0 CMTPOL CMT Output Polarity 6 1 read-write 0 The IRO signal is active-low. #0 1 The IRO signal is active-high. #1 IROL IRO Latch Control 7 1 read-write IROPEN IRO Pin Enable 5 1 read-write 0 The IRO signal is disabled. #0 1 The IRO signal is enabled as output. #1 PPS CMT Primary Prescaler Register 0xA 8 read-write n 0x0 0x0 PPSDIV Primary Prescaler Divider 0 4 read-write 0000 Bus clock * 1 #0000 0001 Bus clock * 2 #0001 0010 Bus clock * 3 #0010 0011 Bus clock * 4 #0011 0100 Bus clock * 5 #0100 0101 Bus clock * 6 #0101 0110 Bus clock * 7 #0110 0111 Bus clock * 8 #0111 1000 Bus clock * 9 #1000 1001 Bus clock * 10 #1001 1010 Bus clock * 11 #1010 1011 Bus clock * 12 #1011 1100 Bus clock * 13 #1100 1101 Bus clock * 14 #1101 1110 Bus clock * 15 #1110 1111 Bus clock * 16 #1111 DCDC DC to DC Converter DCDC 0x0 0x0 0x20 registers n LVD_LVW_DCDC 6 REG0 DCDC REGISTER 0 0x0 32 read-write n 0x0 0x0 DCDC_DISABLE_AUTO_CLK_SWITCH Disable automatic clock switch from internal oscillator to external clock. 1 1 read-write 0 Automatic clock switch feature is enabled #0 1 Automatic clock switch feature is disabled #1 DCDC_IN_DIV_CTRL Controls DCDC_IN voltage divider 10 2 read-write 00 OFF #00 01 DCDC_IN #01 10 DCDC_IN / 2 #10 11 DCDC_IN / 4 #11 DCDC_LESS_I Reduces DCDC current by reducing the analog reference current inside the DCDC Converter 25 1 read-write 0 Use normal current for analog references #0 1 Use reduced current for analog references #1 DCDC_LP_DF_CMP_ENABLE Enable low power differential comparators, to sense lower supply in pulsed mode 9 1 read-write 0 DCDC compare the common mode sense of supply(relative to target value) with DCDC_LP_STATE_HYS_L. When it is lower than DCDC_LP_STATE_HYS_L, re-charge output. #0 1 DCDC compare the lower supply(relative to target value) with DCDC_LP_STATE_HYS_L. When it is lower than DCDC_LP_STATE_HYS_L, re-charge output. This is the recommended configuration to guarantee optimal operation #1 DCDC_LP_STATE_HYS_H Configure the hysteretic upper threshold value in low power mode 19 2 read-write 00 Target voltage value + 0 mV #00 01 Target voltage value + 25 mV #01 10 Target voltage value + 50 mV #10 11 Target voltage value + 75 mV #11 DCDC_LP_STATE_HYS_L Configure the hysteretic lower threshold value in low power mode 17 2 read-write 00 Target voltage value - 0 mV #00 01 Target voltage value - 25 mV #01 10 Target voltage value - 50 mV #10 11 Target voltage value - 75 mV #11 DCDC_PWD_OSC_INT Power down internal oscillator. Only set this bit when 32M crystal oscillator is available. 3 1 read-write 0 Internal oscillator is powered up #0 1 Internal oscillator is powered down #1 DCDC_SEL_CLK Select external clock for DCDC when DCDC_DISABLE_AUTO_CLK_SWITCH is set. 2 1 read-write 0 Internal oscillator is used as DCDC clock #0 1 External oscillator is used as DCDC clock #1 DCDC_STS_DC_OK Status bit to indicate that the DCDC output voltage is stable 31 1 read-only 0 Unstable DCDC output voltage #0 1 Stable DCDC output voltage #1 DCDC_XTALOK_DISABLE Disable xtalok detection circuit 27 1 read-write HYST_LP_CMP_DISABLE Disable hysteresis in low power comparator 22 1 read-write 0 Hysteresis feature is enabled #0 1 Hysteresis feature is disabled #1 HYST_LP_COMP_ADJ Adjust hysteretic value in low power comparator 21 1 read-write 0 Adjustment feature is disabled #0 1 Adjustment feature is enabled #1 OFFSET_RSNS_LP_ADJ Adjust hysteretic value in low power voltage sense 23 1 read-write 0 Adjustment feature is disabled #0 1 Adjustment feature is enabled #1 OFFSET_RSNS_LP_DISABLE Disable hysteresis in low power voltage sense 24 1 read-write 0 Hysteresis feature is enabled #0 1 Hysteresis feature is disabled #1 PSWITCH_STATUS Status bit to indicate PSWITCH status 28 1 read-only 0 PSWITCH is low #0 1 PSWITCH is high #1 PWD_CMP_OFFSET Output range comparator monitors the output voltage of DCDC 26 1 read-write 0 Output range comparator powered up. #0 1 Output range comparator powered down. #1 VLPR_VLPW_CONFIG_DCDC_HP Selects behavior of DCDC in device VLPR and VLPW low power modes 30 1 read-write 0 DCDC works in pulsed mode when SoC is in VLPR / VLPW modes. #0 1 DCDC works in continuous mode when SoC is in VLPR / VLPW modes. #1 VLPS_CONFIG_DCDC_HP Selects behavior of DCDC in device VLPS low power mode 29 1 read-write 0 DCDC works in pulsed mode when SOC is in VLPS modes. #0 1 DCDC works in continuous mode when SOC is in VLPS modes. #1 REG1 DCDC REGISTER 1 0x4 32 read-write n 0x0 0x0 DCDC_LOOPCTRL_CM_HST_THRESH Enable hysteresis in switching converter common mode analog comparators 21 1 read-write DCDC_LOOPCTRL_DF_HST_THRESH Enable hysteresis in switching converter differential mode analog comparators 22 1 read-write DCDC_LOOPCTRL_EN_CM_HYST Enable hysteresis in switching converter common mode analog comparators 23 1 read-write DCDC_LOOPCTRL_EN_DF_HYST Enable hysteresis in switching converter differential mode analog comparators 24 1 read-write POSLIMIT_BUCK_IN Upper limit duty cycle limit in DCDC converter 0 7 read-write REG2 DCDC REGISTER 2 0x8 32 read-write n 0x0 0x0 DCDC_BATTMONITOR_BATT_VAL Software should write the VDCDC_IN in this register measured with an 8 mV LSB resolution through the ADC 16 10 read-write DCDC_BATTMONITOR_EN_BATADJ This bit enables the DCDC to improve efficiency and minimize ripple using the information from the BATT_VAL field 15 1 read-write 0 Disable the usage of the DCDC_BATTMONITOR_BATT_VAL value to calculate DCDC loop control #0 1 Enable the usage of DCDC_BATTMONITOR_BATT_VAL value to calculate DCDC loop control #1 DCDC_LOOPCTRL_EN_RCSCALE The DCDC_LOOPCTRL_EN_RCSCALE reduces the response time of the DCDC to transient loads. 9 2 read-write 00 Default response time #00 01 2 times faster than default #01 10 4 times faster than default #10 DCDC_LOOPCTRL_HYST_SIGN This bit ensures proper switching of DCDC in Pulsed mode and is set in Pulsed mode. 13 1 read-write 0 Hysteresis sign not inverted #0 1 Hysteresis sign inverted (proper switching gauranteed) #1 REG3 DCDC REGISTER 3 0xC 32 read-write n 0x0 0x0 DCDC_MINPWR_DC_HALFCLK Set DCDC clock to half frequency for the continuous mode. 24 1 read-write 0 Normal operation for DCDC clock #0 1 DCDC clock operates at half frequency #1 DCDC_MINPWR_DC_HALFCLK_PULSED Set DCDC clock to half frequency for the Pulsed mode. 21 1 read-write 0 Pulsed mode uses normal operation for DCDC clock #0 1 Pulsed mode uses half frequency DCDC clock operation #1 DCDC_MINPWR_DOUBLE_FETS Use double switch FET for the continuous mode 25 1 read-write 0 Normal operation #0 1 Use Double FET #1 DCDC_MINPWR_DOUBLE_FETS_PULSED Use double switch FET for the Pulsed mode 22 1 read-write 0 Pulsed mode uses normal output configuration #0 1 Pulsed mode uses double FET output configuration #1 DCDC_MINPWR_HALF_FETS Use half switch FET for the continuous mode 26 1 read-write 0 Normal operation #0 1 Use Half FET #1 DCDC_MINPWR_HALF_FETS_PULSED Use half switch FET for the Pulsed mode 23 1 read-write 0 Pulsed mode uses normal output configuration #0 1 Pulsed mode uses half FET output configuration #1 DCDC_VDD1P5CTRL_ADJTN Adjust value of duty cycle when switching between VDD_1P5 and VDD_1P8 17 4 read-write DCDC_VDD1P5CTRL_DISABLE_STEP Disable stepping for VDD_1P5. Must set this bit before enter low power modes. 29 1 read-write 0 VDD_1P5 stepping enabled #0 1 VDD_1P5 stepping disabled #1 DCDC_VDD1P5CTRL_TRG_BUCK Target value of VDD_1P5 in buck mode, 25 mV each step from 0x00 to 0x0F Code VDD_1P8 Output Target (V) 0x00 1 6 5 read-write DCDC_VDD1P8CTRL_DISABLE_STEP Disable stepping for VDD_1P8. Must set this bit before enter low power modes. 30 1 read-write 0 VDD_1P8 stepping enabled #0 1 VDD_1P8 stepping disabled #1 DCDC_VDD1P8CTRL_TRG Target value of VDD_1P8 : 25 mV each step in two ranges, from 0x00 to 0x11 and 0x20 to 0x3F and 50 mV each step in range from 0x12 to 0x1F 0 6 read-write REG4 DCDC REGISTER 4 0x10 32 read-write n 0x0 0x0 DCDC_SW_SHUTDOWN Shut down DCDC in buck mode. DCDC can be turned on by pulling PSWITCH to high momentarily (DCDC Turn on time (TDCDC_ON; refer to the data sheet for specific time). This bit should not be used in buck mode when PSWITCH is tied to DCDC_IN. 0 1 read-write UNLOCK 0x3E77 KEY-Key needed to unlock DCDC_REG4 register 16 16 read-write REG6 DCDC REGISTER 6 0x18 32 read-write n 0x0 0x0 PSWITCH_INT_CLEAR This bit clears the PSWITCH interrupt. 2 1 read-write 0 No effect #0 1 Clear PSWITCH interrupt #1 PSWITCH_INT_FALL_EN Enable falling edge detect for interrupt. 1 1 read-write 0 PSWITCH falling edge interrupt disabled #0 1 PSWITCH falling edge interrupt enabled #1 PSWITCH_INT_MUTE Mask interrupt to SoC, edge detection result can be read from PSIWTCH_INT_STS. 3 1 read-write PSWITCH_INT_RISE_EN Enable rising edge detect for interrupt. 0 1 read-write 0 PSWITCH rising edge interrupt disabled #0 1 PSWITCH rising edge interrupt enabled #1 PSWITCH_INT_STS PSWITCH edge detection interrupt status 31 1 read-only 0 PSWITCH interrupt has not occurred #0 1 PSWITCH interrupt has occurred #1 REG7 DCDC REGISTER 7 0x1C 32 read-write n 0x0 0x0 INTEGRATOR_VALUE Integrator value which can be loaded in pulsed mode 0 19 read-write INTEGRATOR_VALUE_SEL Select the integrator value from above register or saved value in hardware. 19 1 read-write 0 Select the saved value in hardware. #0 1 Select the integrator value in this register. #1 PULSE_RUN_SPEEDUP Enable pulse run speedup 20 1 read-write 0 Pulse run speedup feature disabled #0 1 Pulse run speedup feature enabled #1 DMA0 DMA DMA0 0x0 0x0 0x1080 registers n CDNE Clear DONE Status Bit Register 0x1C 8 write-only n 0x0 0x0 CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 CDNE Clear DONE Bit 0 2 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only n 0x0 0x0 CAEE Clear All Enable Error Interrupts 6 1 write-only CEEI Clear Enable Error Interrupt 0 2 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only n 0x0 0x0 CAER Clear All Enable Requests 6 1 write-only CERQ Clear Enable Request 0 2 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only n 0x0 0x0 CAEI Clear All Error Indicators 6 1 write-only CERR Clear Error Indicator 0 2 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only n 0x0 0x0 CAIR Clear All Interrupt Requests 6 1 write-only CINT Clear Interrupt Request 0 2 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CR Control Register 0x0 32 read-write n 0x0 0x0 ACTIVE DMA Active Status 31 1 read-only 0 eDMA is idle. #0 1 eDMA is executing a channel. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 EDBG Enable Debug 1 1 read-write EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 DCHPRI0 Channel Priority Register 0x103 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 2 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI1 Channel Priority Register 0x102 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 2 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI2 Channel Priority Register 0x101 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 2 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI3 Channel Priority Register 0x100 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 2 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write n 0x0 0x0 EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EEI Enable Error Interrupt Register 0x14 32 read-write n 0x0 0x0 EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 ERQ Enable Request Register 0xC 32 read-write n 0x0 0x0 ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERR Error Register 0x2C 32 read-write n 0x0 0x0 ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ES Error Status Register 0x4 32 read-only n 0x0 0x0 CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 ERRCHN Error Channel Number or Canceled Channel Number 8 2 read-only NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 VLD VLD 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 HRS Hardware Request Status Register 0x34 32 read-only n 0x0 0x0 HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 INT Interrupt Request Register 0x24 32 read-write n 0x0 0x0 INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAEE Sets All Enable Error Interrupts 6 1 write-only SEEI Set Enable Error Interrupt 0 2 write-only SERQ Set Enable Request Register 0x1B 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAER Set All Enable Requests 6 1 write-only SERQ Set Enable Request 0 2 write-only SSRT Set START Bit Register 0x1D 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 SSRT Set START Bit 0 2 write-only TCD0_ATTR TCD Transfer Attributes 0x1006 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x101E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x101E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 2 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x1016 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x1016 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 2 read-write TCD0_CSR TCD Control and Status 0x101C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 2 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD0_DADDR TCD Destination Address 0x1010 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x1008 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x1008 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x1008 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_SADDR TCD Source Address 0x1000 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD0_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x1004 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x1026 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x103E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x103E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 2 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x1036 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x1036 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 2 read-write TCD1_CSR TCD Control and Status 0x103C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 2 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD1_DADDR TCD Destination Address 0x1030 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1038 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x1034 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x1028 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x1028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x1028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_SADDR TCD Source Address 0x1020 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD1_SLAST TCD Last Source Address Adjustment 0x102C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x1024 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x1046 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x105E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x105E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 2 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x1056 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x1056 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 2 read-write TCD2_CSR TCD Control and Status 0x105C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 2 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD2_DADDR TCD Destination Address 0x1050 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1058 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x1054 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x1048 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x1048 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x1048 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_SADDR TCD Source Address 0x1040 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD2_SLAST TCD Last Source Address Adjustment 0x104C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x1044 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x1066 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x107E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x107E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 2 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x1076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x1076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 2 read-write TCD3_CSR TCD Control and Status 0x107C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 2 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD3_DADDR TCD Destination Address 0x1070 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1078 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x1074 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x1068 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x1068 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x1068 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_SADDR TCD Source Address 0x1060 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD3_SLAST TCD Last Source Address Adjustment 0x106C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x1064 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write DMAMUX0 DMAMUX DMAMUX0 0x0 0x0 0x4 registers n CHCFG0 Channel Configuration register 0x3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG1 Channel Configuration register 0x2 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG2 Channel Configuration register 0x1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG3 Channel Configuration register 0x0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 FGPIOA General Purpose Input/Output FGPIO 0x0 0x0 0x18 registers n PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 FGPIOB General Purpose Input/Output FGPIO 0x0 0x0 0x18 registers n PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 FGPIOC General Purpose Input/Output FGPIO 0x0 0x0 0x18 registers n PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 FTFE Flash Memory Interface FTFE 0x0 0x0 0x30 registers n FTFE 5 FACSN Flash Access Segment Number Register 0x2B 8 read-only n 0x0 0x0 NUMSG Number of Segments Indicator 0 8 read-only 1000000 Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes) #1000000 110000 Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes) #110000 FACSS Flash Access Segment Size Register 0x28 8 read-only n 0x0 0x0 SGSIZE Segment Size 0 8 read-only FCCOB0 Flash Common Command Object Registers 0x1A 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB1 Flash Common Command Object Registers 0x13 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB2 Flash Common Command Object Registers 0xD 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB3 Flash Common Command Object Registers 0x8 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB4 Flash Common Command Object Registers 0x40 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB5 Flash Common Command Object Registers 0x35 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB6 Flash Common Command Object Registers 0x2B 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB7 Flash Common Command Object Registers 0x22 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB8 Flash Common Command Object Registers 0x76 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB9 Flash Common Command Object Registers 0x67 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOBA Flash Common Command Object Registers 0x59 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOBB Flash Common Command Object Registers 0x4C 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCNFG Flash Configuration Register 0x1 8 read-write n 0x0 0x0 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 EEERDY For devices with FlexNVM: This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access 0 1 read-only 0 For devices with FlexNVM: FlexRAM is not available for EEPROM operation For devices without FlexNVM: See RAMRDY for availability of programming acceleration RAM #0 1 For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup For devices without FlexNVM: Reserved #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state #1 ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution #1 PFLSH FTFE configuration 2 1 read-only 0 For devices with FlexNVM: FTFE configuration supports one program flash block and one FlexNVM block For devices with program flash only: Reserved #0 1 For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports two program flash blocks #1 RAMRDY RAM Ready 1 1 read-only 0 For devices with FlexNVM: FlexRAM is not available for traditional RAM access For devices without FlexNVM: Programming acceleration RAM is not available #0 1 For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations For devices without FlexNVM: Programming acceleration RAM is available #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 SWAP Swap 3 1 read-only 0 For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0 block is located at relative address 0x0000 #0 1 For devices with program flash only: Program flash 1 block is located at relative address 0x0000 #1 FDPROT Data Flash Protection Register 0x17 8 read-write n 0x0 0x0 DPROT Data Flash Region Protect 0 8 read-write 0 Data Flash region is protected #0 1 Data Flash region is not protected #1 FEPROT EEPROM Protection Register 0x16 8 read-write n 0x0 0x0 EPROT EEPROM Region Protect 0 8 read-write 0 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected #0 1 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected #1 FERCNFG Flash Error Configuration Register 0x2F 8 read-write n 0x0 0x0 DFDIE Double Bit Fault Detect Interrupt Enable 1 1 read-write 0 Double bit fault detect interrupt disabled #0 1 Double bit fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[DFDIF] flag is set. #1 FDFD Force Double Bit Fault Detect 5 1 read-write 0 FERSTAT[DFDIF] sets only if a double bit fault is detected during read access from the platform flash controller #0 1 FERSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set. #1 FERSTAT Flash Error Status Register 0x2E 8 read-write n 0x0 0x0 DFDIF Double Bit Fault Detect Interrupt Flag 1 1 read-write 0 Double bit fault not detected during a valid flash read access from the platform flash controller #0 1 Double bit fault detected (or FERCNFG[FDFD] is set) during a valid flash read access from the platform flash controller #1 FOPT Flash Option Register 0x3 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FPROT0 Program Flash Protection Registers 0x56 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT1 Program Flash Protection Registers 0x43 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT2 Program Flash Protection Registers 0x31 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT3 Program Flash Protection Registers 0x20 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FSEC Flash Security Register 0x2 8 read-only n 0x0 0x0 FSLACC Factory Security Level Access Code 2 2 read-only 00 Factory access granted #00 01 Factory access denied #01 10 Factory access denied #10 11 Factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN Mass Erase Enable Bits 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 00 MCU security status is secure #00 01 MCU security status is secure #01 10 MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) #10 11 MCU security status is secure #11 FSTAT Flash Status Register 0x0 8 read-write n 0x0 0x0 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 FTFE command or EEPROM file system operation in progress #0 1 FTFE command or EEPROM file system operation has completed #1 FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only RDCOLERR FTFE Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 SACCH0 Supervisor-only Access Registers 0xA6 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCH1 Supervisor-only Access Registers 0x83 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCH2 Supervisor-only Access Registers 0x61 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCH3 Supervisor-only Access Registers 0x40 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL0 Supervisor-only Access Registers 0x13C 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL1 Supervisor-only Access Registers 0x115 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL2 Supervisor-only Access Registers 0xEF 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL3 Supervisor-only Access Registers 0xCA 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 XACCH0 Execute-only Access Registers 0x7E 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCH1 Execute-only Access Registers 0x63 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCH2 Execute-only Access Registers 0x49 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCH3 Execute-only Access Registers 0x30 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL0 Execute-only Access Registers 0xF4 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL1 Execute-only Access Registers 0xD5 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL2 Execute-only Access Registers 0xB7 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL3 Execute-only Access Registers 0x9A 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 FTFE_FlashConfig Flash configuration field FTFE_FlashConfig 0x0 0x0 0x10 registers n BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY3 Backdoor Comparison Key 3. 0x0 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only FDPROT Non-volatile D-Flash Protection Register 0xF 8 read-only n 0x0 0x0 DPROT D-Flash Region Protect 0 8 read-only FEPROT Non-volatile EERAM Protection Register 0xE 8 read-only n 0x0 0x0 EPROT no description available 0 8 read-only FOPT Non-volatile Flash Option Register 0xD 8 read-only n 0x0 0x0 LPBOOT0 no description available 0 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. #0 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. #1 LPBOOT1 no description available 4 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. #0 01 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 RESET_PIN_CFG no description available 3 1 read-only 00 RESET pin is disabled following a POR and cannot be enabled as reset function #0 01 RESET_b pin is dedicated #1 FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 NV_BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY3 Backdoor Comparison Key 3. 0x0 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_FDPROT Non-volatile D-Flash Protection Register 0xF 8 read-only n 0x0 0x0 DPROT D-Flash Region Protect 0 8 read-only NV_FEPROT Non-volatile EERAM Protection Register 0xE 8 read-only n 0x0 0x0 EPROT no description available 0 8 read-only NV_FOPT Non-volatile Flash Option Register 0xD 8 read-only n 0x0 0x0 LPBOOT0 no description available 0 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. #0 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. #1 LPBOOT1 no description available 4 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. #0 01 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 RESET_PIN_CFG no description available 3 1 read-only 00 RESET pin is disabled following a POR and cannot be enabled as reset function #0 01 RESET_b pin is dedicated #1 NV_FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FSEC Non-volatile Flash Security Register 0xC 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 GENFSK GENERIC FSK GENFSK 0x0 0x0 0xF80 registers n BITRATE BIT RATE 0x88 32 read-write n 0x0 0x0 BITRATE Bit Rate 0 2 read-write 0 1Mbit/sec #00 1 500Kbit/sec #01 2 250Kbit/sec (not supported if WHITEN_CFG[MANCHESTER_EN]=1) #10 CHANNEL_NUM CHANNEL NUMBER 0x20 32 read-write n 0x0 0x0 CHANNEL_NUM Channel Number 0 7 read-write CRC_CFG CRC CONFIGURATION 0x6C 32 read-write n 0x0 0x0 CRC_BYTE_ORD CRC Byte Order 18 1 read-write 0 LS Byte First #0 1 MS Byte First #1 CRC_REF_IN CRC Reflect In 16 1 read-write 0 do not manipulate input data stream #0 1 reflect each byte in the input stream bitwise #1 CRC_REF_OUT CRC Reflect Out 17 1 read-write 0 do not manipulate CRC result #0 1 CRC result is to be reflected bitwise (operated on entire word) #1 CRC_START_BYTE Configure CRC Start Point 8 4 read-write CRC_SZ CRC Size (in octets) 0 3 read-write CRC_INIT CRC INITIALIZATION 0x70 32 read-write n 0x0 0x0 CRC_SEED CRC Seed Value 0 32 read-write CRC_POLY CRC POLYNOMIAL 0x74 32 read-write n 0x0 0x0 CRC_POLY CRC Polynomial. 0 32 read-write CRC_XOR_OUT CRC XOR OUT 0x78 32 read-write n 0x0 0x0 CRC_XOR_OUT CRC XOR OUT Register 0 32 read-write DSM_CTRL DSM CONTROL 0x40 32 read-write n 0x0 0x0 GEN_SLEEP_REQUEST GENERIC_FSK Deep Sleep Mode Request 0 1 read-write EVENT_TMR EVENT TIMER 0x4 32 read-write n 0x0 0x0 EVENT_TMR Event Timer 0 24 read-write EVENT_TMR_ADD Event Timer Add 25 1 write-only EVENT_TMR_LD Event Timer Load 24 1 write-only H0_CFG H0 CONFIGURATION 0x64 32 read-write n 0x0 0x0 H0_MASK H0 Mask Register 16 16 read-write H0_MATCH H0 Match Register 0 16 read-write H1_CFG H1 CONFIGURATION 0x68 32 read-write n 0x0 0x0 H1_MASK H1 Mask Register 16 16 read-write H1_MATCH H1 Match Register 0 16 read-write IRQ_CTRL IRQ CONTROL 0x0 32 read-write n 0x0 0x0 CRC_IGNORE CRC Ignore 27 1 read-write 0 RX_IRQ will not be asserted for a received packet which fails CRC verification. #0 1 RX_IRQ will be asserted even for a received packet which fails CRC verification. #1 CRC_VALID CRC Valid 31 1 read-only 0 CRC of RX packet is not valid. #0 1 CRC of RX packet is valid. #1 GENERIC_FSK_IRQ_EN GENERIC_FSK_IRQ Master Enable 26 1 read-write 0 All GENERIC_FSK Interrupts are disabled. #0 1 All GENERIC_FSK Interrupts can be enabled. #1 NTW_ADR_IRQ Network Address Match Interrupt 3 1 read-write 0 Network Address Match Interrupt is not asserted. #0 1 Network Address Match Interrupt is asserted. #1 NTW_ADR_IRQ_EN NTW_ADR_IRQ Enable 19 1 read-write 0 Network Address Match Interrupt is not enabled. #0 1 Network Address Match Interrupt is enabled. #1 PLL_UNLOCK_IRQ PLL Unlock Interrupt 6 1 read-write 0 PLL Unlock Interrupt is not asserted. #0 1 PLL Unlock Interrupt is asserted. #1 PLL_UNLOCK_IRQ_EN PLL_UNLOCK_IRQ Enable 22 1 read-write 0 PLL Unlock Interrupt is not enabled. #0 1 PLL Unlock Interrupt is enabled. #1 RX_IRQ RX Interrupt 2 1 read-write 0 RX Interrupt is not asserted. #0 1 RX Interrupt is asserted. #1 RX_IRQ_EN RX_IRQ Enable 18 1 read-write 0 RX Interrupt is not enabled. #0 1 RX Interrupt is enabled. #1 RX_WATERMARK_IRQ RX Watermark Interrupt 8 1 read-write 0 RX Watermark Interrupt is not asserted. #0 1 RX Watermark Interrupt is asserted. #1 RX_WATERMARK_IRQ_EN RX_WATERMARK_IRQ Enable 24 1 read-write 0 RX Watermark Interrupt is not enabled. #0 1 RX Watermark Interrupt is enabled. #1 SEQ_END_IRQ Sequence End Interrupt 0 1 read-write 0 Sequence End Interrupt is not asserted. #0 1 Sequence End Interrupt is asserted. #1 SEQ_END_IRQ_EN SEQ_END_IRQ Enable 16 1 read-write 0 Sequence End Interrupt is not enabled. #0 1 Sequence End Interrupt is enabled. #1 T1_IRQ Timer1 (T1) Compare Interrupt 4 1 read-write 0 Timer1 (T1) Compare Interrupt is not asserted. #0 1 Timer1 (T1) Compare Interrupt is asserted. #1 T1_IRQ_EN T1_IRQ Enable 20 1 read-write 0 Timer1 (T1) Compare Interrupt is not enabled. #0 1 Timer1 (T1) Compare Interrupt is enabled. #1 T2_IRQ Timer2 (T2) Compare Interrupt 5 1 read-write 0 Timer2 (T2) Compare Interrupt is not asserted. #0 1 Timer2 (T2) Compare Interrupt is asserted. #1 T2_IRQ_EN T2_IRQ Enable 21 1 read-write 0 Timer1 (T2) Compare Interrupt is not enabled. #0 1 Timer1 (T2) Compare Interrupt is enabled. #1 TSM_IRQ TSM Interrupt 9 1 read-only 0 TSM0_IRQ and TSM1_IRQ are both clear. #0 1 Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS. #1 TSM_IRQ_EN TSM_IRQ Enable 25 1 read-write 0 TSM Interrupt is not enabled. #0 1 TSM Interrupt is enabled. #1 TX_IRQ TX Interrupt 1 1 read-write 0 TX Interrupt is not asserted. #0 1 TX Interrupt is asserted. #1 TX_IRQ_EN TX_IRQ Enable 17 1 read-write 0 TX Interrupt is not enabled. #0 1 TX Interrupt is enabled. #1 WAKE_IRQ Wake Interrrupt 7 1 read-write 0 Wake Interrupt is not asserted. #0 1 Wake Interrupt is asserted. #1 WAKE_IRQ_EN WAKE_IRQ Enable 23 1 read-write 0 Wake Interrupt is not enabled. #0 1 Wake Interrupt is enabled. #1 NTW_ADR_0 NETWORK ADDRESS 0 0x2C 32 read-write n 0x0 0x0 NTW_ADR_0 Network Address 0 0 32 read-write NTW_ADR_1 NETWORK ADDRESS 1 0x30 32 read-write n 0x0 0x0 NTW_ADR_1 Network Address 1 0 32 read-write NTW_ADR_2 NETWORK ADDRESS 2 0x34 32 read-write n 0x0 0x0 NTW_ADR_2 Network Address 2 0 32 read-write NTW_ADR_3 NETWORK ADDRESS 3 0x38 32 read-write n 0x0 0x0 NTW_ADR_3 Network Address 2 0 32 read-write NTW_ADR_CTRL NETWORK ADDRESS CONTROL 0x28 32 read-write n 0x0 0x0 NTW_ADR0_SZ Network Address 0 Size 8 2 read-write 0 Network Address 0 requires a 8-bit correlation #00 1 Network Address 0 requires a 16-bit correlation #01 2 Network Address 0 requires a 24-bit correlation #10 3 Network Address 0 requires a 32-bit correlation #11 NTW_ADR1_SZ Network Address 1 Size 10 2 read-write 0 Network Address 1 requires a 8-bit correlation #00 1 Network Address 1 requires a 16-bit correlation #01 2 Network Address 1 requires a 24-bit correlation #10 3 Network Address 1 requires a 32-bit correlation #11 NTW_ADR2_SZ Network Address 2 Size 12 2 read-write 0 Network Address 2 requires a 8-bit correlation #00 1 Network Address 2 requires a 16-bit correlation #01 2 Network Address 2 requires a 24-bit correlation #10 3 Network Address 2 requires a 32-bit correlation #11 NTW_ADR3_SZ Network Address 3 Size 14 2 read-write 0 Network Address 3 requires a 8-bit correlation #00 1 Network Address 3 requires a 16-bit correlation #01 2 Network Address 3 requires a 24-bit correlation #10 3 Network Address 3 requires a 32-bit correlation #11 NTW_ADR_EN Network Address Enable 0 4 read-write 0001 Enable Network Address 0 for correlation #0001 0010 Enable Network Address 1 for correlation #0010 0100 Enable Network Address 2 for correlation #0100 1000 Enable Network Address 3 for correlation #1000 NTW_ADR_MCH Network Address Match 4 4 read-only 0001 Network Address 0 has matched #0001 0010 Network Address 1 has matched #0010 0100 Network Address 2 has matched #0100 1000 Network Address 3 has matched #1000 NTW_ADR_THR0 Network Address 0 Threshold 16 3 read-write NTW_ADR_THR1 Network Address 1 Threshold 20 3 read-write NTW_ADR_THR2 Network Address 2 Threshold 24 3 read-write NTW_ADR_THR3 Network Address 3 Threshold 28 3 read-write PACKET_BUFFER_0 PACKET BUFFER 0x700 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1 PACKET BUFFER 0x702 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_10 PACKET BUFFER 0x714 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_100 PACKET BUFFER 0x7C8 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1000 PACKET BUFFER 0xED0 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1001 PACKET BUFFER 0xED2 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1002 PACKET BUFFER 0xED4 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1003 PACKET BUFFER 0xED6 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1004 PACKET BUFFER 0xED8 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1005 PACKET BUFFER 0xEDA 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1006 PACKET BUFFER 0xEDC 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1007 PACKET BUFFER 0xEDE 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1008 PACKET BUFFER 0xEE0 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1009 PACKET BUFFER 0xEE2 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_101 PACKET BUFFER 0x7CA 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1010 PACKET BUFFER 0xEE4 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1011 PACKET BUFFER 0xEE6 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1012 PACKET BUFFER 0xEE8 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1013 PACKET BUFFER 0xEEA 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1014 PACKET BUFFER 0xEEC 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1015 PACKET BUFFER 0xEEE 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1016 PACKET BUFFER 0xEF0 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1017 PACKET BUFFER 0xEF2 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1018 PACKET BUFFER 0xEF4 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1019 PACKET BUFFER 0xEF6 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_102 PACKET BUFFER 0x7CC 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1020 PACKET BUFFER 0xEF8 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1021 PACKET BUFFER 0xEFA 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1022 PACKET BUFFER 0xEFC 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1023 PACKET BUFFER 0xEFE 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1024 PACKET BUFFER 0xF00 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1025 PACKET BUFFER 0xF02 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1026 PACKET BUFFER 0xF04 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1027 PACKET BUFFER 0xF06 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1028 PACKET BUFFER 0xF08 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1029 PACKET BUFFER 0xF0A 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_103 PACKET BUFFER 0x7CE 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1030 PACKET BUFFER 0xF0C 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1031 PACKET BUFFER 0xF0E 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1032 PACKET BUFFER 0xF10 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1033 PACKET BUFFER 0xF12 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1034 PACKET BUFFER 0xF14 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1035 PACKET BUFFER 0xF16 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_1036 PACKET BUFFER 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PACKET_BUFFER_967 PACKET BUFFER 0xE8E 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_968 PACKET BUFFER 0xE90 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_969 PACKET BUFFER 0xE92 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_97 PACKET BUFFER 0x7C2 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_970 PACKET BUFFER 0xE94 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_971 PACKET BUFFER 0xE96 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_972 PACKET BUFFER 0xE98 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_973 PACKET BUFFER 0xE9A 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_974 PACKET BUFFER 0xE9C 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_975 PACKET BUFFER 0xE9E 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_976 PACKET BUFFER 0xEA0 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_977 PACKET BUFFER 0xEA2 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_978 PACKET BUFFER 0xEA4 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_979 PACKET BUFFER 0xEA6 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_98 PACKET BUFFER 0x7C4 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_980 PACKET BUFFER 0xEA8 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_981 PACKET BUFFER 0xEAA 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_982 PACKET BUFFER 0xEAC 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_983 PACKET BUFFER 0xEAE 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_984 PACKET BUFFER 0xEB0 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_985 PACKET BUFFER 0xEB2 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_986 PACKET BUFFER 0xEB4 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_987 PACKET BUFFER 0xEB6 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_988 PACKET BUFFER 0xEB8 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_989 PACKET BUFFER 0xEBA 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_99 PACKET BUFFER 0x7C6 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_990 PACKET BUFFER 0xEBC 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_991 PACKET BUFFER 0xEBE 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_992 PACKET BUFFER 0xEC0 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_993 PACKET BUFFER 0xEC2 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_994 PACKET BUFFER 0xEC4 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_995 PACKET BUFFER 0xEC6 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_996 PACKET BUFFER 0xEC8 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_997 PACKET BUFFER 0xECA 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_998 PACKET BUFFER 0xECC 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_BUFFER_999 PACKET BUFFER 0xECE 16 read-write n 0x0 0x0 PACKET_BUFFER PACKET BUFFER RAM 0 16 read-write PACKET_CFG PACKET CONFIGURATION 0x60 32 read-write n 0x0 0x0 H0_FAIL H0 Violated Status Bit 30 1 read-only H0_SZ H0 Size 16 5 read-write H1_FAIL H1 Violated Status Bit 29 1 read-only H1_SZ H1 Size 24 5 read-write LENGTH_ADJ Length Adjustment 8 8 read-write LENGTH_ADJ_UNSIGNED Length Adjustment Unsigned Enabled 21 1 read-write 0 Hardware interprets LENGTH_ADJ as a signed integer (default) #0 1 Hardware interprets LENGTH_ADJ as a unsigned integer #1 LENGTH_BIT_ORD LENGTH Bit Order 5 1 read-write 0 LS Bit First #0 1 MS Bit First #1 LENGTH_FAIL Maximum Length Violated Status Bit 31 1 read-only LENGTH_SZ LENGTH Size 0 5 read-write SYNC_ADDR_SZ Sync Address Size 6 2 read-write PART_ID PART ID 0x44 32 read-only n 0x0 0x0 PART_ID Part ID 0 8 read-only PB_PARTITION PACKET BUFFER PARTITION POINT 0x8C 32 read-write n 0x0 0x0 PB_PARTITION Packet Buffer Partition Point 0 11 read-write RX_WATERMARK RECEIVE WATERMARK 0x3C 32 read-write n 0x0 0x0 BYTE_COUNTER Byte Counter 16 13 read-only RX_WATERMARK Receive Watermark 0 13 read-write T1_CMP T1 COMPARE 0x8 32 read-write n 0x0 0x0 T1_CMP Timer1 (T1) Compare Value 0 24 read-write T1_CMP_EN Timer1 (T1) Compare Enable 24 1 read-write T2_CMP T2 COMPARE 0xC 32 read-write n 0x0 0x0 T2_CMP Timer2 (T2) Compare Value 0 24 read-write T2_CMP_EN Timer2 (T2) Compare Enable 24 1 read-write TIMESTAMP TIMESTAMP 0x10 32 read-only n 0x0 0x0 TIMESTAMP Received Packet Timestamp 0 24 read-only TX_POWER TRANSMIT POWER 0x24 32 read-write n 0x0 0x0 TX_POWER Transmit Power 0 6 read-write WHITEN_CFG WHITENER CONFIGURATION 0x7C 32 read-write n 0x0 0x0 MANCHESTER_EN Configure for Manchester Encoding/Decoding 12 1 read-write 0 Disable Manchester encoding (TX) and decoding (RX) #0 1 Enable Manchester encoding (TX) and decoding (RX) #1 MANCHESTER_INV Configure for Inverted Manchester Encoding 13 1 read-write 0 Manchester coding as per 802.3 #0 1 Manchester coding as per 802.3 but with the encoding signal inverted #1 MANCHESTER_START Configure Manchester Encoding Start Point 14 1 read-write 0 Start Manchester coding at start-of-payload #0 1 Start Manchester coding at start-of-header #1 WHITEN_B4_CRC Congifure for Whitening-before-CRC 3 1 read-write 0 CRC before whiten/de-whiten #0 1 Whiten/de-whiten before CRC #1 WHITEN_END Configure end-of-whitening 2 1 read-write 0 end whiten at end-of-payload #0 1 end whiten at end-of-crc #1 WHITEN_INIT Initialization Value for Whitening/De-whitening 16 9 read-write WHITEN_PAYLOAD_REINIT Configure for Whitener re-initialization 6 1 read-write 0 Don't re-initialize Whitener LFSR at start-of-payload #0 1 Re-initialize Whitener LFSR at start-of-payload #1 WHITEN_POLY_TYPE Whiten Polynomial Type 4 1 read-write WHITEN_REF_IN Whiten Reflect Input 5 1 read-write WHITEN_SIZE Length of Whitener LFSR 8 4 read-write WHITEN_START Configure Whitener Start Point 0 2 read-write 0 no whitening #00 1 start whitening at start-of-H0 #01 2 start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR #10 3 start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR #11 WHITEN_POLY WHITENER POLYNOMIAL 0x80 32 read-write n 0x0 0x0 WHITEN_POLY Whitener Polynomial 0 9 read-write WHITEN_SZ_THR WHITENER SIZE THRESHOLD 0x84 32 read-write n 0x0 0x0 LENGTH_MAX Maximum Length for Received Packets 16 7 read-write REC_BAD_PKT Receive Bad Packets 23 1 read-write 0 packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed #0 1 packets which fail H0, H1, or LENGTH_MAX are received in their entirety #1 WHITEN_SZ_THR Whitener Size Threshold 0 12 read-write XCVR_CFG TRANSCEIVER CONFIGURATION 0x1C 32 read-write n 0x0 0x0 PREAMBLE_SZ Preamble Size 4 3 read-write RX_DEWHITEN_DIS RX De-Whitening Disable 1 1 read-write RX_WARMUP Receive Warmup Time 16 8 read-only STOP_POSTPONE_ON_AA Postpone Stop Command Timeout On Access Address Match Enable 3 1 read-write 0 STOP Abort will occur on RX_STOP_T1 or RX_STOP_T1 Event Timer match, regardless of ntw_adr_matched #0 1 STOP Abort will be deferred on RX_STOP_T1 or RX_STOP_T1 Event Timer match, if ntw_adr_matched is asserted otherwise the RX_STOP Abort will occur immediately #1 SW_CRC_EN Software CRC Enable 2 1 read-write TX_WARMUP Transmit Warmup Time 8 8 read-only TX_WHITEN_DIS TX Whitening Disable 0 1 read-write XCVR_CTRL TRANSCEIVER CONTROL 0x14 32 read-write n 0x0 0x0 CMDDEC_CS Command Decode 24 3 read-only LENGTH_EXT Extracted Length Field 8 11 read-only SEQCMD Sequence Commands 0 4 read-write 0x0 No Action #0000 0x1 TX Start Now #0001 0x2 TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #0010 0x3 TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #0011 0x4 TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress #0100 0x5 RX Start Now #0101 0x6 RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #0110 0x7 RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #0111 0x8 RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) #1000 0x9 RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) #1001 0xA RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress #1010 0xB Abort All - Cancels all pending events and abort any sequence-in-progress #1011 XCVR_BUSY Transceiver Busy 31 1 read-only 0 IDLE #0 1 BUSY #1 XCVR_STS TRANSCEIVER STATUS 0x18 32 read-only n 0x0 0x0 CRC_VALID CRC Valid Indicator 15 1 read-only 0 CRC is not valid for RX packet. #0 1 CRC is valid for RX packet. #1 LQI Link Quality Indicator 24 8 read-only LQI_VALID LQI Valid Indicator 14 1 read-only 0 LQI is not yet valid for RX packet. #0 1 LQI is valid for RX packet. #1 RSSI Received Signal Stength Indicator, in dBm 16 8 read-only RX_IN_PROGRESS RX in Progress Status 11 1 read-only RX_IN_SEARCH RX Search Status 10 1 read-only RX_IN_WARMDN RX Warmdown Status 12 1 read-only RX_IN_WARMUP RX Warmup Status 9 1 read-only RX_START_T1_PEND RX T1 Start Pending Status 5 1 read-only RX_START_T2_PEND RX T2 Start Pending Status 6 1 read-only RX_STOP_T1_PEND RX T1 Stop Pending Status 7 1 read-only RX_STOP_T2_PEND RX T2 Start Pending Status 8 1 read-only TX_IN_PROGRESS TX in Progress Status 3 1 read-only TX_IN_WARMDN TX Warmdown Status 4 1 read-only TX_IN_WARMUP TX Warmup Status 2 1 read-only TX_START_T1_PEND TX T1 Start Pending Status 0 1 read-only TX_START_T2_PEND TX T2 Start Pending Status 1 1 read-only GPIOA General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTA 30 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO0 Port Clear Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO1 Port Clear Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO10 Port Clear Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO11 Port Clear Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO12 Port Clear Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO13 Port Clear Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO14 Port Clear Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO15 Port Clear Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO16 Port Clear Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO17 Port Clear Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO18 Port Clear Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO19 Port Clear Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO2 Port Clear Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO20 Port Clear Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO21 Port Clear Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO22 Port Clear Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO23 Port Clear Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO24 Port Clear Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO25 Port Clear Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO26 Port Clear Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO27 Port Clear Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO28 Port Clear Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO29 Port Clear Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO3 Port Clear Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO30 Port Clear Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO31 Port Clear Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO4 Port Clear Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO5 Port Clear Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO6 Port Clear Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO7 Port Clear Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO8 Port Clear Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO9 Port Clear Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD0 Port Data Direction 0 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD1 Port Data Direction 1 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD10 Port Data Direction 10 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD11 Port Data Direction 11 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD12 Port Data Direction 12 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD13 Port Data Direction 13 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD14 Port Data Direction 14 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD15 Port Data Direction 15 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD16 Port Data Direction 16 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD17 Port Data Direction 17 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD18 Port Data Direction 18 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD19 Port Data Direction 19 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD2 Port Data Direction 2 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD20 Port Data Direction 20 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD21 Port Data Direction 21 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD22 Port Data Direction 22 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD23 Port Data Direction 23 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD24 Port Data Direction 24 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD25 Port Data Direction 25 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD26 Port Data Direction 26 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD27 Port Data Direction 27 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD28 Port Data Direction 28 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD29 Port Data Direction 29 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD3 Port Data Direction 3 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD30 Port Data Direction 30 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD31 Port Data Direction 31 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD4 Port Data Direction 4 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD5 Port Data Direction 5 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD6 Port Data Direction 6 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD7 Port Data Direction 7 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD8 Port Data Direction 8 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD9 Port Data Direction 9 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI0 Port Data Input 0 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI1 Port Data Input 1 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI10 Port Data Input 10 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI11 Port Data Input 11 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI12 Port Data Input 12 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI13 Port Data Input 13 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI14 Port Data Input 14 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI15 Port Data Input 15 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI16 Port Data Input 16 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI17 Port Data Input 17 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI18 Port Data Input 18 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI19 Port Data Input 19 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI2 Port Data Input 2 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI20 Port Data Input 20 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI21 Port Data Input 21 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI22 Port Data Input 22 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI23 Port Data Input 23 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI24 Port Data Input 24 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI25 Port Data Input 25 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI26 Port Data Input 26 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI27 Port Data Input 27 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI28 Port Data Input 28 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI29 Port Data Input 29 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI3 Port Data Input 3 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI30 Port Data Input 30 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI31 Port Data Input 31 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI4 Port Data Input 4 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI5 Port Data Input 5 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI6 Port Data Input 6 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI7 Port Data Input 7 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI8 Port Data Input 8 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI9 Port Data Input 9 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO0 Port Data Output 0 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO1 Port Data Output 1 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO10 Port Data Output 10 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO11 Port Data Output 11 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO12 Port Data Output 12 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO13 Port Data Output 13 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO14 Port Data Output 14 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO15 Port Data Output 15 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO16 Port Data Output 16 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO17 Port Data Output 17 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO18 Port Data Output 18 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO19 Port Data Output 19 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO2 Port Data Output 2 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO20 Port Data Output 20 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO21 Port Data Output 21 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO22 Port Data Output 22 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO23 Port Data Output 23 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO24 Port Data Output 24 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO25 Port Data Output 25 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO26 Port Data Output 26 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO27 Port Data Output 27 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO28 Port Data Output 28 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO29 Port Data Output 29 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO3 Port Data Output 3 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO30 Port Data Output 30 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO31 Port Data Output 31 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO4 Port Data Output 4 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO5 Port Data Output 5 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO6 Port Data Output 6 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO7 Port Data Output 7 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO8 Port Data Output 8 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO9 Port Data Output 9 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO0 Port Set Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO1 Port Set Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO10 Port Set Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO11 Port Set Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO12 Port Set Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO13 Port Set Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO14 Port Set Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO15 Port Set Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO16 Port Set Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO17 Port Set Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO18 Port Set Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO19 Port Set Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO2 Port Set Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO20 Port Set Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO21 Port Set Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO22 Port Set Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO23 Port Set Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO24 Port Set Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO25 Port Set Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO26 Port Set Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO27 Port Set Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO28 Port Set Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO29 Port Set Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO3 Port Set Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO30 Port Set Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO31 Port Set Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO4 Port Set Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO5 Port Set Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO6 Port Set Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO7 Port Set Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO8 Port Set Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO9 Port Set Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO0 Port Toggle Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO1 Port Toggle Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO10 Port Toggle Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO11 Port Toggle Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO12 Port Toggle Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO13 Port Toggle Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO14 Port Toggle Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO15 Port Toggle Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO16 Port Toggle Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO17 Port Toggle Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO18 Port Toggle Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO19 Port Toggle Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO2 Port Toggle Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO20 Port Toggle Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO21 Port Toggle Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO22 Port Toggle Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO23 Port Toggle Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO24 Port Toggle Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO25 Port Toggle Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO26 Port Toggle Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO27 Port Toggle Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO28 Port Toggle Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO29 Port Toggle Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO3 Port Toggle Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO30 Port Toggle Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO31 Port Toggle Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO4 Port Toggle Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO5 Port Toggle Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO6 Port Toggle Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO7 Port Toggle Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO8 Port Toggle Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO9 Port Toggle Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOB General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTB_PORTC 31 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO0 Port Clear Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO1 Port Clear Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO10 Port Clear Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO11 Port Clear Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO12 Port Clear Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO13 Port Clear Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO14 Port Clear Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO15 Port Clear Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO16 Port Clear Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO17 Port Clear Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO18 Port Clear Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO19 Port Clear Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO2 Port Clear Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO20 Port Clear Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO21 Port Clear Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO22 Port Clear Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO23 Port Clear Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO24 Port Clear Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO25 Port Clear Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO26 Port Clear Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO27 Port Clear Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO28 Port Clear Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO29 Port Clear Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO3 Port Clear Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO30 Port Clear Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO31 Port Clear Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO4 Port Clear Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO5 Port Clear Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO6 Port Clear Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO7 Port Clear Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO8 Port Clear Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO9 Port Clear Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD0 Port Data Direction 0 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD1 Port Data Direction 1 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD10 Port Data Direction 10 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD11 Port Data Direction 11 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD12 Port Data Direction 12 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD13 Port Data Direction 13 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD14 Port Data Direction 14 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD15 Port Data Direction 15 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD16 Port Data Direction 16 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD17 Port Data Direction 17 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD18 Port Data Direction 18 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD19 Port Data Direction 19 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD2 Port Data Direction 2 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD20 Port Data Direction 20 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD21 Port Data Direction 21 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD22 Port Data Direction 22 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD23 Port Data Direction 23 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD24 Port Data Direction 24 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD25 Port Data Direction 25 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD26 Port Data Direction 26 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD27 Port Data Direction 27 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD28 Port Data Direction 28 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD29 Port Data Direction 29 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD3 Port Data Direction 3 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD30 Port Data Direction 30 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD31 Port Data Direction 31 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD4 Port Data Direction 4 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD5 Port Data Direction 5 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD6 Port Data Direction 6 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD7 Port Data Direction 7 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD8 Port Data Direction 8 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD9 Port Data Direction 9 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI0 Port Data Input 0 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI1 Port Data Input 1 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI10 Port Data Input 10 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI11 Port Data Input 11 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI12 Port Data Input 12 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI13 Port Data Input 13 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI14 Port Data Input 14 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI15 Port Data Input 15 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI16 Port Data Input 16 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI17 Port Data Input 17 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI18 Port Data Input 18 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI19 Port Data Input 19 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI2 Port Data Input 2 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI20 Port Data Input 20 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI21 Port Data Input 21 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI22 Port Data Input 22 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI23 Port Data Input 23 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI24 Port Data Input 24 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI25 Port Data Input 25 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI26 Port Data Input 26 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI27 Port Data Input 27 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI28 Port Data Input 28 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI29 Port Data Input 29 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI3 Port Data Input 3 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI30 Port Data Input 30 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI31 Port Data Input 31 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI4 Port Data Input 4 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI5 Port Data Input 5 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI6 Port Data Input 6 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI7 Port Data Input 7 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI8 Port Data Input 8 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI9 Port Data Input 9 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO0 Port Data Output 0 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO1 Port Data Output 1 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO10 Port Data Output 10 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO11 Port Data Output 11 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO12 Port Data Output 12 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO13 Port Data Output 13 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO14 Port Data Output 14 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO15 Port Data Output 15 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO16 Port Data Output 16 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO17 Port Data Output 17 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO18 Port Data Output 18 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO19 Port Data Output 19 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO2 Port Data Output 2 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO20 Port Data Output 20 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO21 Port Data Output 21 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO22 Port Data Output 22 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO23 Port Data Output 23 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO24 Port Data Output 24 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO25 Port Data Output 25 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO26 Port Data Output 26 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO27 Port Data Output 27 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO28 Port Data Output 28 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO29 Port Data Output 29 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO3 Port Data Output 3 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO30 Port Data Output 30 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO31 Port Data Output 31 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO4 Port Data Output 4 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO5 Port Data Output 5 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO6 Port Data Output 6 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO7 Port Data Output 7 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO8 Port Data Output 8 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO9 Port Data Output 9 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO0 Port Set Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO1 Port Set Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO10 Port Set Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO11 Port Set Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO12 Port Set Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO13 Port Set Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO14 Port Set Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO15 Port Set Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO16 Port Set Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO17 Port Set Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO18 Port Set Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO19 Port Set Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO2 Port Set Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO20 Port Set Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO21 Port Set Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO22 Port Set Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO23 Port Set Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO24 Port Set Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO25 Port Set Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO26 Port Set Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO27 Port Set Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO28 Port Set Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO29 Port Set Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO3 Port Set Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO30 Port Set Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO31 Port Set Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO4 Port Set Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO5 Port Set Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO6 Port Set Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO7 Port Set Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO8 Port Set Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO9 Port Set Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO0 Port Toggle Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO1 Port Toggle Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO10 Port Toggle Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO11 Port Toggle Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO12 Port Toggle Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO13 Port Toggle Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO14 Port Toggle Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO15 Port Toggle Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO16 Port Toggle Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO17 Port Toggle Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO18 Port Toggle Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO19 Port Toggle Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO2 Port Toggle Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO20 Port Toggle Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO21 Port Toggle Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO22 Port Toggle Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO23 Port Toggle Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO24 Port Toggle Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO25 Port Toggle Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO26 Port Toggle Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO27 Port Toggle Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO28 Port Toggle Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO29 Port Toggle Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO3 Port Toggle Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO30 Port Toggle Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO31 Port Toggle Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO4 Port Toggle Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO5 Port Toggle Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO6 Port Toggle Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO7 Port Toggle Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO8 Port Toggle Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO9 Port Toggle Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOC General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTB_PORTC 31 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO0 Port Clear Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO1 Port Clear Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO10 Port Clear Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO11 Port Clear Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO12 Port Clear Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO13 Port Clear Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO14 Port Clear Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO15 Port Clear Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO16 Port Clear Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO17 Port Clear Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO18 Port Clear Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO19 Port Clear Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO2 Port Clear Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO20 Port Clear Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO21 Port Clear Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO22 Port Clear Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO23 Port Clear Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO24 Port Clear Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO25 Port Clear Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO26 Port Clear Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO27 Port Clear Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO28 Port Clear Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO29 Port Clear Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO3 Port Clear Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO30 Port Clear Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO31 Port Clear Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO4 Port Clear Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO5 Port Clear Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO6 Port Clear Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO7 Port Clear Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO8 Port Clear Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PTCO9 Port Clear Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD0 Port Data Direction 0 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD1 Port Data Direction 1 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD10 Port Data Direction 10 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD11 Port Data Direction 11 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD12 Port Data Direction 12 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD13 Port Data Direction 13 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD14 Port Data Direction 14 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD15 Port Data Direction 15 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD16 Port Data Direction 16 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD17 Port Data Direction 17 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD18 Port Data Direction 18 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD19 Port Data Direction 19 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD2 Port Data Direction 2 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD20 Port Data Direction 20 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD21 Port Data Direction 21 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD22 Port Data Direction 22 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD23 Port Data Direction 23 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD24 Port Data Direction 24 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD25 Port Data Direction 25 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD26 Port Data Direction 26 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD27 Port Data Direction 27 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD28 Port Data Direction 28 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD29 Port Data Direction 29 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD3 Port Data Direction 3 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD30 Port Data Direction 30 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD31 Port Data Direction 31 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD4 Port Data Direction 4 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD5 Port Data Direction 5 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD6 Port Data Direction 6 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD7 Port Data Direction 7 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD8 Port Data Direction 8 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDD9 Port Data Direction 9 1 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI0 Port Data Input 0 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI1 Port Data Input 1 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI10 Port Data Input 10 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI11 Port Data Input 11 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI12 Port Data Input 12 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI13 Port Data Input 13 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI14 Port Data Input 14 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI15 Port Data Input 15 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI16 Port Data Input 16 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI17 Port Data Input 17 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI18 Port Data Input 18 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI19 Port Data Input 19 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI2 Port Data Input 2 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI20 Port Data Input 20 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI21 Port Data Input 21 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI22 Port Data Input 22 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI23 Port Data Input 23 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI24 Port Data Input 24 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI25 Port Data Input 25 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI26 Port Data Input 26 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI27 Port Data Input 27 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI28 Port Data Input 28 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI29 Port Data Input 29 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI3 Port Data Input 3 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI30 Port Data Input 30 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI31 Port Data Input 31 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI4 Port Data Input 4 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI5 Port Data Input 5 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI6 Port Data Input 6 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI7 Port Data Input 7 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI8 Port Data Input 8 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDI9 Port Data Input 9 1 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO0 Port Data Output 0 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO1 Port Data Output 1 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO10 Port Data Output 10 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO11 Port Data Output 11 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO12 Port Data Output 12 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO13 Port Data Output 13 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO14 Port Data Output 14 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO15 Port Data Output 15 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO16 Port Data Output 16 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO17 Port Data Output 17 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO18 Port Data Output 18 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO19 Port Data Output 19 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO2 Port Data Output 2 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO20 Port Data Output 20 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO21 Port Data Output 21 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO22 Port Data Output 22 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO23 Port Data Output 23 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO24 Port Data Output 24 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO25 Port Data Output 25 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO26 Port Data Output 26 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO27 Port Data Output 27 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO28 Port Data Output 28 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO29 Port Data Output 29 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO3 Port Data Output 3 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO30 Port Data Output 30 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO31 Port Data Output 31 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO4 Port Data Output 4 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO5 Port Data Output 5 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO6 Port Data Output 6 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO7 Port Data Output 7 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO8 Port Data Output 8 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PDO9 Port Data Output 9 1 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO0 Port Set Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO1 Port Set Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO10 Port Set Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO11 Port Set Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO12 Port Set Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO13 Port Set Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO14 Port Set Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO15 Port Set Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO16 Port Set Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO17 Port Set Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO18 Port Set Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO19 Port Set Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO2 Port Set Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO20 Port Set Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO21 Port Set Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO22 Port Set Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO23 Port Set Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO24 Port Set Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO25 Port Set Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO26 Port Set Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO27 Port Set Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO28 Port Set Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO29 Port Set Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO3 Port Set Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO30 Port Set Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO31 Port Set Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO4 Port Set Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO5 Port Set Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO6 Port Set Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO7 Port Set Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO8 Port Set Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTSO9 Port Set Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO0 Port Toggle Output 0 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO1 Port Toggle Output 1 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO10 Port Toggle Output 10 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO11 Port Toggle Output 11 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO12 Port Toggle Output 12 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO13 Port Toggle Output 13 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO14 Port Toggle Output 14 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO15 Port Toggle Output 15 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO16 Port Toggle Output 16 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO17 Port Toggle Output 17 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO18 Port Toggle Output 18 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO19 Port Toggle Output 19 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO2 Port Toggle Output 2 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO20 Port Toggle Output 20 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO21 Port Toggle Output 21 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO22 Port Toggle Output 22 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO23 Port Toggle Output 23 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO24 Port Toggle Output 24 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO25 Port Toggle Output 25 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO26 Port Toggle Output 26 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO27 Port Toggle Output 27 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO28 Port Toggle Output 28 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO29 Port Toggle Output 29 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO3 Port Toggle Output 3 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO30 Port Toggle Output 30 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO31 Port Toggle Output 31 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO4 Port Toggle Output 4 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO5 Port Toggle Output 5 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO6 Port Toggle Output 6 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO7 Port Toggle Output 7 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO8 Port Toggle Output 8 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTTO9 Port Toggle Output 9 1 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 I2C0 Inter-Integrated Circuit I2C 0x0 0x0 0xD registers n I2C0 8 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 SAD SMBus Address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave Address 0 3 read-write ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write n 0x0 0x0 FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range Slave Address 1 7 read-write S I2C Status register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 S2 I2C Status register 2 0xC 8 read-write n 0x0 0x0 DFEN Double Buffer Enable 2 1 read-write 0 Disables the double buffer mode; clock stretch is enabled. #0 1 Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. #1 EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT SSLT[7:0] 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 I2C1 Inter-Integrated Circuit I2C 0x0 0x0 0xD registers n I2C1 9 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 SAD SMBus Address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave Address 0 3 read-write ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write n 0x0 0x0 FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range Slave Address 1 7 read-write S I2C Status register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 S2 I2C Status register 2 0xC 8 read-write n 0x0 0x0 DFEN Double Buffer Enable 2 1 read-write 0 Disables the double buffer mode; clock stretch is enabled. #0 1 Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. #1 EMPTY Empty flag 0 1 read-only 0 Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. #0 1 Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. #1 ERROR Error flag 1 1 read-write 0 The buffer is not full and all write/read operations have no errors. #0 1 There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT SSLT[7:0] 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 LLWU Low leakage wakeup unit LLWU 0x0 0x0 0xA registers n LLWU 7 F1 LLWU Flag 1 register 0x5 8 read-write n 0x0 0x0 WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wake-up source #0 1 LLWU_P3 input was a wake-up source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 F2 LLWU Flag 2 register 0x6 8 read-write n 0x0 0x0 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 F3 LLWU Flag 3 register 0x7 8 read-only n 0x0 0x0 MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 register 0x8 8 read-write n 0x0 0x0 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 FILT2 LLWU Pin Filter 2 register 0x9 8 read-write n 0x0 0x0 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 FILTSEL Filter Pin Select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 ME LLWU Module Enable register 0x4 8 read-write n 0x0 0x0 WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 PE1 LLWU Pin Enable 1 register 0x0 8 read-write n 0x0 0x0 WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write n 0x0 0x0 WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write n 0x0 0x0 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write n 0x0 0x0 WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 LPTMR0 Low Power Timer LPTMR0 0x0 0x0 0x10 registers n LPTMR0 28 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 16 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 LPUART0 Universal Asynchronous Receiver/Transmitter LPUART 0x0 0x0 0x20 registers n LPUART0_LPUART1 12 BAUD LPUART Baud Rate Register 0x0 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 OSR Oversampling Ratio 24 5 read-write RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 CTRL LPUART Control Register 0x8 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 DATA LPUART Data Register 0xC 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FIFO LPUART FIFO Register 0x18 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 010 Receive FIFO/Buffer depth = 4 datawords. #010 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 010 Transmit FIFO/Buffer depth = 4 datawords. #010 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 MATCH LPUART Match Address Register 0x10 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS assertion is configured by the RTSWATER field #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 STAT LPUART Status Register 0x4 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 WATER LPUART Watermark Register 0x1C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 8 read-only RXWATER Receive Watermark 16 8 read-write TXCOUNT Transmit Counter 8 8 read-only TXWATER Transmit Watermark 0 8 read-write LPUART1 Universal Asynchronous Receiver/Transmitter LPUART 0x0 0x0 0x20 registers n LPUART0_LPUART1 12 BAUD LPUART Baud Rate Register 0x0 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 OSR Oversampling Ratio 24 5 read-write RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 CTRL LPUART Control Register 0x8 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 DATA LPUART Data Register 0xC 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FIFO LPUART FIFO Register 0x18 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 010 Receive FIFO/Buffer depth = 4 datawords. #010 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 010 Transmit FIFO/Buffer depth = 4 datawords. #010 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 MATCH LPUART Match Address Register 0x10 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x14 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS assertion is configured by the RTSWATER field #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 STAT LPUART Status Register 0x4 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 WATER LPUART Watermark Register 0x1C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 8 read-only RXWATER Receive Watermark 16 8 read-write TXCOUNT Transmit Counter 8 8 read-only TXWATER Transmit Watermark 0 8 read-write LTC0 LTC LTC0 0x0 0x0 0x7F4 registers n LTC0 23 AADSZ AAD Size Register 0x58 32 read-write n 0x0 0x0 AADSZ AAD size in Bytes, mod 16 0 4 read-write AL AAD Last 31 1 read-write CHAVID CHA Version ID Register 0x4F8 32 read-only n 0x0 0x0 AESREV AES Revision Number 0 4 read-only AESVID AES Version ID 4 4 read-only COM Command Register 0x30 32 read-write n 0x0 0x0 AES Reset AESA 1 1 write-only 0 Do Not Reset #0 1 Reset AES Accelerator #1 ALL Reset All Internal Logic 0 1 write-only 0 Do Not Reset #0 1 Reset all CHAs in use by this CCB. #1 CTL Control Register 0x34 32 read-write n 0x0 0x0 CIS Context Register Input Byte Swap 22 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 COS Context Register Output Byte Swap 23 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 IFE Input FIFO DMA Enable 8 1 read-write 0 DMA Request and Done signals disabled for the Input FIFO. #0 1 DMA Request and Done signals enabled for the Input FIFO. #1 IFR Input FIFO DMA Request Size 9 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 IFS Input FIFO Byte Swap 16 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 IM Interrupt Mask 0 1 read-write 0 Interrupt not masked. #0 1 Interrupt masked #1 KAL Key Register Access Lock 31 1 read-write 0 Key Register is readable. #0 1 Key Register is not readable. #1 KIS Key Register Input Byte Swap 20 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 KOS Key Register Output Byte Swap 21 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 OFE Output FIFO DMA Enable 12 1 read-write 0 DMA Request and Done signals disabled for the Output FIFO. #0 1 DMA Request and Done signals enabled for the Output FIFO. #1 OFR Output FIFO DMA Request Size 13 1 read-write 0 DMA request size is 1 entry. #0 1 DMA request size is 4 entries. #1 OFS Output FIFO Byte Swap 17 1 read-write 0 Do Not Byte Swap Data. #0 1 Byte Swap Data. #1 CTX_0 Context Register 0x100 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_1 Context Register 0x104 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_10 Context Register 0x128 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_11 Context Register 0x12C 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_12 Context Register 0x130 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_13 Context Register 0x134 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_2 Context Register 0x108 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_3 Context Register 0x10C 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_4 Context Register 0x110 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_5 Context Register 0x114 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_6 Context Register 0x118 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_7 Context Register 0x11C 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_8 Context Register 0x120 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CTX_9 Context Register 0x124 32 read-write n 0x0 0x0 CTX CTX 0 32 read-write CW Clear Written Register 0x40 32 read-write n 0x0 0x0 CCR Clear the Context Register 5 1 write-only CDS Clear the Data Size Register 2 1 write-only CICV Clear the ICV Size Register 3 1 write-only CIF Clear Input FIFO 31 1 write-only CKR Clear the Key Register 6 1 write-only CM Clear the Mode Register 0 1 write-only COF Clear Output FIFO 30 1 write-only DS Data Size Register 0x10 32 read-write n 0x0 0x0 DS Data Size 0 12 read-write ESTA Error Status Register 0x4C 32 read-only n 0x0 0x0 CL1 algorithms 8 4 read-only 0000 General Error #0000 0001 AES #0001 ERRID1 Error ID 1 0 4 read-only 0001 Mode Error #0001 0010 Data Size Error #0010 0011 Key Size Error #0011 0110 Data Arrived out of Sequence Error #0110 1010 ICV Check Failed #1010 1011 Internal Hardware Failure #1011 1100 CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) #1100 1111 Invalid Crypto Engine Selected #1111 FIFOSTA FIFO Status Register 0x7C0 32 read-only n 0x0 0x0 IFF Input FIFO Full 15 1 read-only IFL Input FIFO Level 0 7 read-only OFF Output FIFO Full 31 1 read-only OFL Output FIFO Level 16 7 read-only ICVS ICV Size Register 0x18 32 read-write n 0x0 0x0 ICVS ICV Size, in Bytes 0 5 read-write IFIFO Input Data FIFO 0x7E0 32 write-only n 0x0 0x0 IFIFO IFIFO 0 32 write-only KEY_0 Key Registers 0x200 32 read-write n 0x0 0x0 KEY KEY 0 32 read-write KEY_1 Key Registers 0x204 32 read-write n 0x0 0x0 KEY KEY 0 32 read-write KEY_2 Key Registers 0x208 32 read-write n 0x0 0x0 KEY KEY 0 32 read-write KEY_3 Key Registers 0x20C 32 read-write n 0x0 0x0 KEY KEY 0 32 read-write KS Key Size Register 0x8 32 read-write n 0x0 0x0 KS Key Size 0 5 write-only MD Mode Register 0x0 32 read-write n 0x0 0x0 AAI Additional Algorithm information 4 9 read-write ALG Algorithm 16 8 read-write 00010000 AES #10000 AS Algorithm State 2 2 read-write 00 Update #00 01 Initialize #01 10 Finalize #10 11 Initialize/Finalize #11 ENC Encrypt/Decrypt. 0 1 read-write 0 Decrypt. #0 1 Encrypt. #1 ICV_TEST ICV Checking / Test AES fault detection. 1 1 read-write OFIFO Output Data FIFO 0x7F0 32 read-only n 0x0 0x0 OFIFO Output FIFO 0 32 read-only STA Status Register 0x48 32 read-write n 0x0 0x0 AB AESA Busy 1 1 read-only 0 AESA Idle #0 1 AESA Busy. #1 DI Done Interrupt 16 1 read-write EI Error Interrupt 20 1 read-only 0 Not Error. #0 1 Error Interrupt. #1 VID1 Version ID Register 0x4F0 32 read-only n 0x0 0x0 IP_ID ID(0x0034). 16 16 read-only MAJ_REV Major revision number. 8 8 read-only MIN_REV Minor revision number. 0 8 read-only VID2 Version ID 2 Register 0x4F4 32 read-only n 0x0 0x0 ARCH_ERA Architectural ERA. 8 8 read-only ECO_REV ECO revision number. 0 8 read-only MCG Multipurpose Clock Generator module MCG 0x0 0x0 0xE registers n MCG 27 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write n 0x0 0x0 ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write n 0x0 0x0 ATCVL ATM Compare Value Low 0 8 read-write C1 MCG Control 1 Register 0x0 8 read-write n 0x0 0x0 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL is selected. #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . #110 111 If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . #111 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 C2 MCG Control 2 Register 0x1 8 read-write n 0x0 0x0 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 FCFTRIM Fast Internal Reference Clock Fine Trim 6 1 read-write HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 LP Low Power Select 1 1 read-write 0 FLL is not disabled in bypass modes. #0 1 FLL is disabled in bypass modes (lower power) #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 C3 MCG Control 3 Register 0x2 8 read-write n 0x0 0x0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write n 0x0 0x0 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write C5 MCG Control 5 Register 0x4 8 read-only n 0x0 0x0 C6 MCG Control 6 Register 0x5 8 read-write n 0x0 0x0 CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled. #0 1 Generate an interrupt or a reset request (see MCG_C2[LOCRE0]) on loss of external clock. #1 C7 MCG Control 7 Register 0xC 8 read-write n 0x0 0x0 OSCSEL MCG OSC Clock Select 0 1 read-write 0 Selects Oscillator (OSCCLK). #0 1 Selects 32 kHz RTC Oscillator. #1 C8 MCG Control 8 Register 0xD 8 read-write n 0x0 0x0 CME1 Clock Monitor Enable1 5 1 read-write 0 External clock monitor is disabled for RTC clock. #0 1 External clock monitor is enabled for RTC clock. #1 LOCRE1 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of RTC external reference clock. #0 1 Generate a reset request on a loss of RTC external reference clock #1 LOCS1 RTC Loss of Clock Status 0 1 read-write 0 Loss of RTC has not occur. #0 1 Loss of RTC has occur #1 S MCG Status Register 0x6 8 read-only n 0x0 0x0 CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 OSCINIT0 OSC Initialization 1 1 read-only SC MCG Status and Control Register 0x8 8 read-write n 0x0 0x0 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 MCM Core Platform Miscellaneous Control Module MCM 0x0 0x8 0x3C registers n CPO Compute Operation Control Register 0x40 32 read-write n 0x0 0x0 CPOACK Compute Operation Acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOREQ Compute Operation Request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOWOI Compute Operation Wake-up on Interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 PLACR Platform Control Register 0xC 32 read-write n 0x0 0x0 ARB Arbitration select 9 1 read-write 0 Fixed-priority arbitration for the crossbar masters #0 1 Round-robin arbitration for the crossbar masters #1 CFCC Clear Flash Controller Cache 10 1 write-only DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only n 0x0 0x0 AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only n 0x0 0x0 ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent. #0 1 A bus slave connection to AXBS input port n is present. #1 MTB Micro Trace Buffer MTB 0x0 0x0 0x1000 registers n AUTHSTAT Authentication Status Register 0xFB8 32 read-only n 0x0 0x0 BIT0 Connected to DBGEN. 0 1 read-only BIT1 BIT1 1 1 read-only BIT2 BIT2 2 1 read-only BIT3 BIT3 3 1 read-only BASE MTB Base Register 0xC 32 read-only n 0x0 0x0 BASEADDR BASEADDR 0 32 read-only COMPID0 Component ID Register 0x1FE0 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID1 Component ID Register 0x2FD4 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID2 Component ID Register 0x3FCC 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID3 Component ID Register 0x4FC8 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only DEVICEARCH Device Architecture Register 0xFBC 32 read-only n 0x0 0x0 DEVICEARCH DEVICEARCH 0 32 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only n 0x0 0x0 DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only n 0x0 0x0 DEVICETYPID DEVICETYPID 0 32 read-only FLOW MTB Flow Register 0x8 32 read-write n 0x0 0x0 AUTOHALT AUTOHALT 1 1 read-write AUTOSTOP AUTOSTOP 0 1 read-write WATERMARK WATERMARK[28:0] 3 29 read-write LOCKACCESS Lock Access Register 0xFB0 32 read-only n 0x0 0x0 LOCKACCESS Hardwired to 0x0000_0000 0 32 read-only LOCKSTAT Lock Status Register 0xFB4 32 read-only n 0x0 0x0 LOCKSTAT LOCKSTAT 0 32 read-only MASTER MTB Master Register 0x4 32 read-write n 0x0 0x0 EN Main Trace Enable 31 1 read-write HALTREQ Halt Request 9 1 read-write MASK Mask 0 5 read-write RAMPRIV RAM Privilege 8 1 read-write SFRWPRIV Special Function Register Write Privilege 7 1 read-write TSTARTEN Trace Start Input Enable 5 1 read-write TSTOPEN Trace Stop Input Enable 6 1 read-write MODECTRL Integration Mode Control Register 0xF00 32 read-only n 0x0 0x0 MODECTRL MODECTRL 0 32 read-only PERIPHID0 Peripheral ID Register 0x5F08 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID1 Peripheral ID Register 0x6EEC 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID2 Peripheral ID Register 0x7ED4 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID3 Peripheral ID Register 0x8EC0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID4 Peripheral ID Register 0x1FA0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID5 Peripheral ID Register 0x2F74 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID6 Peripheral ID Register 0x3F4C 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID7 Peripheral ID Register 0x4F28 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only POSITION MTB Position Register 0x0 32 read-write n 0x0 0x0 POINTER Trace Packet Address Pointer[28:0] 3 29 read-write WRAP WRAP 2 1 read-write TAGCLEAR Claim TAG Clear Register 0xFA4 32 read-only n 0x0 0x0 TAGCLEAR TAGCLEAR 0 32 read-only TAGSET Claim TAG Set Register 0xFA0 32 read-only n 0x0 0x0 TAGSET TAGSET 0 32 read-only MTBDWT MTB data watchpoint and trace MTBDWT 0x0 0x0 0x1000 registers n COMP0 MTB_DWT Comparator Register 0x40 32 read-write n 0x0 0x0 COMP Reference value for comparison 0 32 read-write COMP1 MTB_DWT Comparator Register 0x70 32 read-write n 0x0 0x0 COMP Reference value for comparison 0 32 read-write COMPID0 Component ID Register 0x1FE0 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID1 Component ID Register 0x2FD4 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID2 Component ID Register 0x3FCC 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID3 Component ID Register 0x4FC8 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only CTRL MTB DWT Control Register 0x0 32 read-only n 0x0 0x0 DWTCFGCTRL DWT configuration controls 0 28 read-only NUMCMP Number of comparators 28 4 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only n 0x0 0x0 DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only n 0x0 0x0 DEVICETYPID DEVICETYPID 0 32 read-only FCT0 MTB_DWT Comparator Function Register 0 0x28 32 read-write n 0x0 0x0 DATAVADDR0 Data Value Address 0 12 4 read-write DATAVMATCH Data Value Match 8 1 read-write 0 Perform address comparison. #0 1 Perform data value comparison. #1 DATAVSIZE Data Value Size 10 2 read-write 00 Byte. #00 01 Halfword. #01 10 Word. #10 11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. #11 FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 FCT1 MTB_DWT Comparator Function Register 1 0x38 32 read-write n 0x0 0x0 FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 MASK0 MTB_DWT Comparator Mask Register 0x48 32 read-write n 0x0 0x0 MASK MASK 0 5 read-write MASK1 MTB_DWT Comparator Mask Register 0x7C 32 read-write n 0x0 0x0 MASK MASK 0 5 read-write PERIPHID0 Peripheral ID Register 0x5F08 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID1 Peripheral ID Register 0x6EEC 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID2 Peripheral ID Register 0x7ED4 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID3 Peripheral ID Register 0x8EC0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID4 Peripheral ID Register 0x1FA0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID5 Peripheral ID Register 0x2F74 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID6 Peripheral ID Register 0x3F4C 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID7 Peripheral ID Register 0x4F28 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only TBCTRL MTB_DWT Trace Buffer Control Register 0x200 32 read-write n 0x0 0x0 ACOMP0 Action based on Comparator 0 match 0 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. #1 ACOMP1 Action based on Comparator 1 match 1 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. #1 NUMCOMP Number of Comparators 28 4 read-only PIT PIT PIT 0x0 0x0 0x120 registers n CVAL0 Current Timer Value Register 0x104 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL1 Current Timer Value Register 0x114 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only LDVAL0 Timer Load Value Register 0x100 32 read-write n 0x0 0x0 TSV Timer Start Value 0 32 read-write LDVAL1 Timer Load Value Register 0x110 32 read-write n 0x0 0x0 TSV Timer Start Value 0 32 read-write LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only n 0x0 0x0 LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only n 0x0 0x0 LTL Life Timer value 0 32 read-only MCR PIT Module Control Register 0x0 32 read-write n 0x0 0x0 FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable for PIT 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 TCTRL0 Timer Control Register 0x108 32 read-write n 0x0 0x0 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt is requested whenever TIF is set. #1 TCTRL1 Timer Control Register 0x118 32 read-write n 0x0 0x0 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt is requested whenever TIF is set. #1 TFLG0 Timer Flag Register 0x10C 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TFLG1 Timer Flag Register 0x11C 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 PMC Power Management Controller PMC 0x0 0x0 0x3 registers n LVD_LVW_DCDC 6 LVDSC1 Low Voltage Detect Status And Control 1 register 0x0 8 read-write n 0x0 0x0 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write n 0x0 0x0 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 REGSC Regulator Status And Control register 0x2 8 read-write n 0x0 0x0 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 BGEN Bandgap Enable In VLPx Operation 4 1 read-write 0 Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. #0 1 Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 VLPO VLPx Option 6 1 read-write 0 Operating frequencies and MCG clocking modes are restricted during VLPx modes as listed in the Power Management chapter. #0 1 If BGEN is also set, operating frequencies and MCG clocking modes are unrestricted during VLPx modes. Note that flash access frequency is still restricted however. #1 PORTA PORT PORT 0x0 0x0 0xA4 registers n GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register 16 0x40 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register 17 0x44 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register 18 0x48 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register 19 0x4C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register 2 0x8 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTB PORT PORT 0x0 0x0 0xA4 registers n GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register 16 0x40 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register 17 0x44 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register 18 0x48 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register 2 0x8 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register 3 0xC 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTC PORT PORT 0x0 0x0 0xA4 registers n GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register 16 0x40 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register 17 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register 18 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register 19 0x4C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register 2 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register 3 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register 4 0x10 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register 5 0x14 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register 6 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register 7 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 1000 Alternative 8 (chip-specific). #1000 1001 Alternative 9 (chip-specific). #1001 1010 Alternative 10 (chip-specific). #1010 1011 Alternative 11 (chip-specific). #1011 1100 Alternative 12 (chip-specific). #1100 1101 Alternative 13 (chip-specific). #1101 1110 Alternative 14 (chip-specific). #1110 1111 Alternative 15 (chip-specific). #1111 PE Pull Enable 1 1 read-write PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 RCM Reset Control Module RCM 0x0 0x0 0x6 registers n RPFC Reset Pin Filter Control register 0x4 8 read-write n 0x0 0x0 RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write n 0x0 0x0 RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 SRS0 System Reset Status Register 0 0x0 8 read-only n 0x0 0x0 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SRS1 System Reset Status Register 1 0x1 8 read-only n 0x0 0x0 LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 RFSYS System register file RFSYS 0x0 0x0 0x20 registers n REG0 Register file register 0x0 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG1 Register file register 0x4 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG2 Register file register 0xC 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG3 Register file register 0x18 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG4 Register file register 0x28 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG5 Register file register 0x3C 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG6 Register file register 0x54 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG7 Register file register 0x70 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write ROM System ROM ROM 0x0 0x0 0x1000 registers n COMPID0 Component ID Register 0x1FE0 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID1 Component ID Register 0x2FD4 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID2 Component ID Register 0x3FCC 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID3 Component ID Register 0x4FC8 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only ENTRY0 Entry 0x0 32 read-only n 0x0 0x0 ENTRY ENTRY 0 32 read-only ENTRY1 Entry 0x4 32 read-only n 0x0 0x0 ENTRY ENTRY 0 32 read-only ENTRY2 Entry 0xC 32 read-only n 0x0 0x0 ENTRY ENTRY 0 32 read-only PERIPHID0 Peripheral ID Register 0x5F08 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID1 Peripheral ID Register 0x6EEC 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID2 Peripheral ID Register 0x7ED4 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID3 Peripheral ID Register 0x8EC0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID4 Peripheral ID Register 0x1FA0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID5 Peripheral ID Register 0x2F74 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID6 Peripheral ID Register 0x3F4C 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID7 Peripheral ID Register 0x4F28 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only SYSACCESS System Access Register 0xFCC 32 read-only n 0x0 0x0 SYSACCESS SYSACCESS 0 32 read-only TABLEMARK End of Table Marker Register 0xC 32 read-only n 0x0 0x0 MARK MARK 0 32 read-only RSIM RSIM RSIM 0x0 0x0 0x130 registers n ANA_TEST Radio Analog Test Registers 0x128 32 read-write n 0x0 0x0 XTAL_OUT_BUF_EN XTAL Output Buffer Enable 4 1 read-write ANA_TRIM Radio Analog Trim Registers 0x12C 32 read-write n 0x0 0x0 BB_LDO_LS_SPARE rmap_bb_ldo_ls_spare_hv[1:0] 0 2 read-write BB_LDO_LS_TRIM rmap_bb_ldo_ls_trim_hv[2:0] 3 3 read-write 0 1.20 V (Default) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_LDO_XO_SPARE rmap_bb_ldo_xo_spare_hv[1:0] 6 2 read-write BB_LDO_XO_TRIM rmap_bb_ldo_xo_trim_hv[2:0] 8 3 read-write 0 1.20 V (Default) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_XTAL_SPARE rmap_bb_xtal_spare_hv[4:0] 11 5 read-write BB_XTAL_TRIM rmap_bb_xtal_trim_hv[7:0] 16 8 read-write BG_1V_TRIM rmap_bg_1v_trim_hv[3:0] 24 4 read-write 0 954.14 mV #0000 1 959.26 mV #0001 2 964.38 mV #0010 3 969.5 mV #0011 4 974.6 mV #0100 5 979.7 mV #0101 6 984.8 mV #0110 7 989.9 mV #0111 8 995 mV (Default) #1000 9 1 V #1001 10 1.005 V #1010 11 1.01 V #1011 12 1.015 V #1100 13 1.02 V #1101 14 1.025 V #1110 15 1.031 V #1111 BG_IBIAS_5U_TRIM rmap_bg_ibias_5u_trim_hv[3:0] 28 4 read-write 0 3.55 uA #0000 1 3.73 uA #0001 2 4.04 uA #0010 3 4.22 uA #0011 4 4.39 uA #0100 5 4.57 uA #0101 6 4.89 uA #0110 7 5.06 (Default) #0111 8 5.23 uA #1000 9 5.41 uA #1001 10 5.72 uA #1010 11 5.9 uA #1011 12 6.07 uA #1100 13 6.25 uA #1101 14 6.56 uA #1110 15 6.74 uA #1111 CONTROL Radio System Control 0x0 32 read-write n 0x0 0x0 ALLOW_DFT_RESETS Allow the DFT Reset Pin to Reset the Radio 30 1 read-write BLE_RF_OSC_REQ_EN BLE Ref Osc (Sysclk) Request Enable 0 1 read-write BLE_RF_OSC_REQ_INT BLE Ref Osc (Sysclk) Request Interrupt Flag 5 1 read-write BLE_RF_OSC_REQ_INT_EN BLE Ref Osc (Sysclk) Request Interrupt Enable 4 1 read-write BLE_RF_OSC_REQ_STAT BLE Ref Osc (Sysclk) Request Status 1 1 read-only BLOCK_RADIO_OUTPUTS Block Radio Outputs 29 1 read-write BLOCK_SOC_RESETS Block SoC Resets of the Radio 28 1 read-write RADIO_GASKET_BYPASS_OVRD Radio Gasket Bypass Override 13 1 read-write 0 XCVR and Link Layer Register Clock is the RF Ref Osc Clock #0 1 XCVR and Link Layer Register Clock is the SoC IPG Clock #1 RADIO_GASKET_BYPASS_OVRD_EN Radio Gasket Bypass Override Enable 12 1 read-write RADIO_RAM_ACCESS_OVRD Radio RAM Access Override 19 1 read-write RADIO_RAM_ACCESS_OVRD_EN Radio RAM Access Override Enable 18 1 read-write RADIO_RESET_BIT Software Reset for the Radio 31 1 read-write RF_OSC_EN RF Ref Osc Enable Select 8 4 read-write 0000 RF Ref Osc will be controlled by the SoC, external pin, or a link layer #0000 0001 RF Ref Osc on in Run/Wait #0001 0011 RF Ref Osc on in Stop #0011 0111 RF Ref Osc on in VLPR/VLPW #0111 1111 RF Ref Osc on in VLPS #1111 RF_OSC_READY RF Ref Osc Ready 24 1 read-only RF_OSC_READY_OVRD RF Ref Osc Ready Override 26 1 read-write RF_OSC_READY_OVRD_EN RF Ref Osc Ready Override Enable 25 1 read-write RSIM_DSM_EXIT BLE Force Deep Sleep Mode Exit 20 1 read-write RSIM_STOP_ACK_OVRD Stop Acknowledge Override 23 1 read-write RSIM_STOP_ACK_OVRD_EN Stop Acknowledge Override Enable 22 1 read-write DSM_CONTROL Deep Sleep Timer Control 0x104 32 read-write n 0x0 0x0 DSM_GEN_FINISHED Generic FSK Deep Sleep Time Finished 10 1 read-only DSM_GEN_READY Generic FSK Ready for Deep Sleep Mode 8 1 read-only DSM_TIMER_CLR Deep Sleep Mode Timer Clear 27 1 read-write DSM_TIMER_EN Deep Sleep Mode Timer Enable 31 1 read-write GEN_DEEP_SLEEP_STATUS Generic FSK Link Layer Deep Sleep Mode Status 9 1 read-only GEN_FSM_STATE GEN Deep Sleep State Machine State 16 5 read-only GEN_SLEEP_REQUEST Generic FSK Link Layer Deep Sleep Requested 12 1 read-only GEN_SYSCLK_INTERRUPT_EN Generic FSK Link Layer RF OSC Request Interrupt Enable 14 1 read-write GEN_SYSCLK_REQ Generic FSK Link Layer RF OSC Request Status 13 1 read-only GEN_SYSCLK_REQUEST_EN Enable Generic FSK Link Layer to Request RF OSC 11 1 read-write GEN_SYSCLK_REQ_INT Interrupt Flag from an Generic FSK Link Layer RF OSC Request 15 1 read-write DSM_OSC_OFFSET Deep Sleep Wakeup Time Offset 0x108 32 read-write n 0x0 0x0 DSM_OSC_STABILIZE_TIME Deep Sleep Wakeup RF OSC Stabilize Time 0 10 read-write DSM_TIMER Deep Sleep Timer 0x100 32 read-only n 0x0 0x0 DSM_TIMER Deep Sleep Mode Timer 0 24 read-only DSM_WAKEUP Deep Sleep Wakeup Sequence 0x4 32 read-write n 0x0 0x0 ACTIVE_WARNING Deep Sleep Wakeup RF Active Warning Time 24 6 read-write COARSE_DELAY Deep Sleep Wakeup Coarse Delay Time 16 4 read-write FINE_DELAY Deep Sleep Wakeup Fine Delay Time 0 6 read-write GEN_SLEEP Generic FSK Link Layer Sleep Time 0x11C 32 read-write n 0x0 0x0 GEN_SLEEP_TIME Generic FSK Link Layer Sleep Time 0 24 read-write GEN_WAKE Generic FSK Link Layer Wake Time 0x120 32 read-write n 0x0 0x0 GEN_WAKE_TIME Generic FSK Link Layer Wake Time 0 24 read-write MAC_LSB Radio MAC Address 0xC 32 read-only n 0x0 0x0 MAC_ADDR_LSB Radio MAC Address LSB 0 32 read-only MAC_MSB Radio MAC Address 0x8 32 read-only n 0x0 0x0 MAC_ADDR_MSB Radio MAC Address MSB 0 8 read-only MISC Radio Miscellaneous 0x10 32 read-write n 0x0 0x0 RADIO_VERSION Radio Version ID number 24 8 read-write RF_OSC_CTRL Radio Oscillator Control 0x124 32 read-write n 0x0 0x0 BB_XTAL_ALC_COUNT_SEL rmap_bb_xtal_alc_count_sel_hv[1:0] 0 2 read-write 0 2048 (64 us @ 32 MHz) #00 1 4096 (128 us @ 32 MHz) #01 2 8192 (256 us @ 32 MHz) #10 3 16384 (512 us @ 32 MHz) #11 BB_XTAL_ALC_ON rmap_bb_xtal_alc_on_hv 2 1 read-write BB_XTAL_COMP_BIAS rmap_bb_xtal_comp_bias_hv[4:0] 4 5 read-write BB_XTAL_DC_COUP_MODE_EN rmap_bb_xtal_dc_coup_mode_en_hv 9 1 read-write BB_XTAL_DIAGSEL rmap_bb_xtal_diagsel_hv 10 1 read-write BB_XTAL_DIG_CLK_ON rmap_bb_xtal_dig_clk_on_hv 11 1 read-write BB_XTAL_GM rmap_bb_xtal_gm_hv[4:0] 12 5 read-write BB_XTAL_ON_OVRD rmap_bb_xtal_on_ovrd_hv 17 1 read-write BB_XTAL_ON_OVRD_ON rmap_bb_xtal_on_ovrd_on_hv 18 1 read-write 0 rfctrl_bb_xtal_on_hv is asserted #0 1 rfctrl_bb_xtal_on_ovrd_hv is asserted #1 BB_XTAL_READY_COUNT_SEL rmap_bb_xtal_ready_count_sel_hv[1:0] 20 2 read-write 0 1024 counts (32 us @ 32 MHz) #00 1 2048 (64 us @ 32 MHz) #01 2 4096 (128 us @ 32 MHz) #10 3 8192 (256 us @ 32 MHz) #11 RADIO_EXT_OSC_OVRD Radio External Request for RF OSC Override 28 1 read-write RADIO_EXT_OSC_OVRD_EN Radio External Request for RF OSC Override Enable 29 1 read-write RADIO_EXT_OSC_RF_EN_SEL Radio External Request for RF OSC Select 27 1 read-write RF_NOT_ALLOWED_OVRD RF Not Allowed Override 30 1 read-write RF_NOT_ALLOWED_OVRD_EN RF Not Allowed Override Enable 31 1 read-write RF_OSC_BYPASS_EN RF Ref Osc Bypass Enable 3 1 read-write SW_CONFIG Radio Software Configuration 0x18 32 read-write n 0x0 0x0 BLOCK_EXT_OSC_PWR_REQ Block External Requests for RF OSC from starting a Radio Power Wakeup Sequence 31 1 read-write IPP_IBE_DFT_RESET IPP_IBE_DFT_RESET 10 1 read-write IPP_IBE_RF_EXT_OSC_EN IPP_IBE_RF_EXT_OSC_EN 9 1 read-write IPP_IBE_RF_NOT_ALLOWED IPP_IBE_RF_NOT_ALLOWED 8 1 read-write IPP_OBE_BLE_EARLY_WARNING IPP_OBE_BLE_EARLY_WARNING 27 1 read-write IPP_OBE_RF_ACTIVE IPP_OBE_RF_ACTIVE 26 1 read-write IPP_OBE_RF_OSC_EN IPP_OBE_RF_OSC_EN 11 1 read-write IPP_OBE_RF_PRIORITY IPP_OBE_RF_PRIORITY 24 1 read-write IPP_OBE_RF_STATUS IPP_OBE_RF_STATUS 25 1 read-write RADIO_BLE_EARLY_WARNING_SEL Radio BLE_EARLY_WARNING Select 14 1 read-write RADIO_CONFIGURED_POR_RESET Radio Configuration Bit, cleared by Radio Power On Reset 0 1 read-write RADIO_CONFIGURED_SYS_RESET Radio Configuration Bit, cleared by Radio System Reset 1 1 read-write RADIO_DFT_RESET_SEL Radio DFT_RESET Select 13 1 read-write RADIO_RF_NOT_ALLOWED_SEL Radio RF_NOT_ALLOWED Select 12 1 read-write RF_ACTIVE_ENDS_WITH_TSM RF_ACTIVE clearing mechanism 20 1 read-only RF_OSC_EN_OVRD Radio Osc Enable Override 6 1 read-write RF_OSC_EN_OVRD_EN Radio Osc Enable Override Enable 7 1 read-write RSIM_RF_ACTIVE_OVRD RF Active Internal Override 4 1 read-write RSIM_RF_ACTIVE_OVRD_EN RF Active Internal Override Enable 5 1 read-write SW_RF_ACTIVE_BIT Software RF_ACTIVE Control Bit 22 1 read-write SW_RF_ACTIVE_EN Software RF_ACTIVE Control Enable 23 1 read-only SW_RF_ACTIVE_ENDS_WITH_TSM Software RF_ACTIVE clearing mechanism 21 1 read-only WIFI_COEXIST_1 RF_ACTIVE Source 16 1 read-only WIFI_COEXIST_2 RF_STATUS Source 17 1 read-only WIFI_COEXIST_3 RF_EARLY_WARNING Source 18 1 read-only RTC Secure Real Time Clock RTC 0x0 0x0 0x20 registers n RTC 4 RTC_Seconds 21 CR RTC Control Register 0x10 32 read-write n 0x0 0x0 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 SC16P Oscillator 16pF Load Configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF Load Configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF Load Configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF Load Configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 SWR Software Reset 0 1 read-write 0 No effect. #0 1 Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. #1 WPS Wakeup Pin Select 4 1 read-write 0 Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. #0 1 Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 WPON Wakeup Pin On 7 1 read-write 0 No effect. #0 1 If the wakeup pin is enabled, then the wakeup pin will assert. #1 LR RTC Lock Register 0x18 32 read-write n 0x0 0x0 CRL Control Register Lock 4 1 read-write 0 Control Register is locked and writes are ignored. #0 1 Control Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock Register is locked and writes are ignored. #0 1 Lock Register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 TCL Time Compensation Lock 3 1 read-write 0 Time Compensation Register is locked and writes are ignored. #0 1 Time Compensation Register is not locked and writes complete as normal. #1 SR RTC Status Register 0x14 32 read-write n 0x0 0x0 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAR RTC Time Alarm Register 0x8 32 read-write n 0x0 0x0 TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write n 0x0 0x0 CIC Compensation Interval Counter 24 8 read-only CIR Compensation Interval Register 8 8 read-write TCR Time Compensation Register 0 8 read-write 0 Time Prescaler Register overflows every 32768 clock cycles. #0 1 Time Prescaler Register overflows every 32767 clock cycles. #1 10000000 Time Prescaler Register overflows every 32896 clock cycles. #10000000 1111111 Time Prescaler Register overflows every 32641 clock cycles. #1111111 11111111 Time Prescaler Register overflows every 32769 clock cycles. #11111111 TCV Time Compensation Value 16 8 read-only TPR RTC Time Prescaler Register 0x4 32 read-write n 0x0 0x0 TPR Time Prescaler Register 0 16 read-write TSR RTC Time Seconds Register 0x0 32 read-write n 0x0 0x0 TSR Time Seconds Register 0 32 read-write SIM System Integration Module SIM 0x0 0x0 0x1108 registers n CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write n 0x0 0x0 OUTDIV1 Clock 1 Output Divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV4 Clock 4 Output Divider value 16 3 read-write 000 Divide-by-1. #000 001 Divide-by-2. #001 010 Divide-by-3. #010 011 Divide-by-4. #011 100 Divide-by-5. #100 101 Divide-by-6. #101 110 Divide-by-7. #110 111 Divide-by-8. #111 COPC COP Control Register 0x1100 32 read-write n 0x0 0x0 COPCLKS COP Clock Select 1 1 read-write 0 COP configured for short timeout #0 1 COP configured for long timeout #1 COPCLKSEL COP Clock Select 6 2 read-write 00 LPO clock (1 kHz) #00 01 MCGIRCLK #01 10 OSCERCLK #10 11 Bus clock #11 COPDBGEN COP Debug Enable 5 1 read-write 0 COP is disabled and the counter is reset in Debug mode #0 1 COP is enabled in Debug mode #1 COPSTPEN COP Stop Enable 4 1 read-write 0 COP is disabled and the counter is reset in Stop modes #0 1 COP is enabled in Stop modes #1 COPT COP Watchdog Timeout 2 2 read-write 00 COP disabled #00 01 COP timeout after 25 cycles for short timeout or 213 cycles for long timeout #01 10 COP timeout after 28 cycles for short timeout or 216 cycles for long timeout #10 11 COP timeout after 210 cycles for short timeout or 218 cycles for long timeout #11 COPW COP Windowed Mode 0 1 read-write 0 Normal mode #0 1 Windowed mode #1 FCFG1 Flash Configuration Register 1 0x104C 32 read-write n 0x0 0x0 DEPART FlexNVM partition 8 4 read-only EESIZE EEPROM Size 16 4 read-only 0001 8 KB #0001 0010 4 KB #0010 0011 2 KB #0011 0100 1 KB #0100 0101 512 bytes #0101 0110 256 bytes #0110 0111 128 bytes #0111 1000 64 bytes #1000 1001 32 bytes #1001 FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled. #0 1 Flash is disabled. #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Doze mode. #0 1 Flash is disabled for the duration of Doze mode. #1 NVMSIZE FlexNVM Size 28 4 read-only 0000 0 KB #0000 1001 256 KB, 16 KB protection region #1001 1111 256 KB, 16 KB protection region #1111 PFSIZE Program Flash Size 24 4 read-only 1001 256 KB of program flash memory #1001 1011 512 KB of program flash memory #1011 FCFG2 Flash Configuration Register 2 0x1050 32 read-only n 0x0 0x0 MAXADDR0 Max Address block 0 24 7 read-only MAXADDR1 This field concatenated with leading zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1) 16 7 read-only PFLSH Program flash only 23 1 read-only 0 Device supports FlexNVM. #0 1 Program Flash only, device does not support FlexNVM. #1 SWAPPFLSH Swap program flash 31 1 read-only 0 Swap is not active. #0 1 Swap is active. #1 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write n 0x0 0x0 CMP Comparator Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CMT CMT Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C1 I2C1 Clock Gate Control 7 1 read-write 0 Clock disabled #0 1 Clock enabled #1 VREF VREF Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write n 0x0 0x0 BTLL BTLL System Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DCDC DCDC Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 GEN_FSK Generic FSK enabled 31 1 read-write 0 GFSK CGC bit disabled. #0 1 GFSK CGC bit enabled. #1 LPTMR Low Power Timer Access Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 LPUART0 LPUART0 Clock Gate Control 20 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPUART1 LPUART1 Clock Gate Control 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LTC LTC Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PHYDIG PHY Digital Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RSIM RSIM Clock Gate Control 25 1 read-only SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write n 0x0 0x0 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXCAN0 FLEXCAN0 Clock Gate Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 RTC RTC Access Control 29 1 read-write 0 Access and interrupts disabled #0 1 Access and interrupts enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM0 TPM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM1 TPM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TPM2 TPM2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TRNG TRNG Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write n 0x0 0x0 DMA DMA Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SDID System Device Identification Register 0x1024 32 read-only n 0x0 0x0 DIEID Device Die Number 7 5 read-only FAMID Kinetis family ID 28 4 read-only 0011 KW3x Family (BTLE) #0011 PINID Pin count Identification 0 4 read-only 0011 40-pin #0011 0100 48-pin #0100 REVID Device Revision Number 12 4 read-only SERIESID Kinetis Series ID 20 4 read-only 0101 KW family #0101 SRAMSIZE System SRAM Size 16 4 read-only 0111 64 KB #0111 SUBFAMID Kinetis Sub-Family ID. 24 3 read-only 101 KWx5 Sub family #101 110 KWx6 Subfamily #110 SOPT1 System Options Register 1 0x0 32 read-write n 0x0 0x0 OSC32KOUT 32K oscillator clock output 16 2 read-write 00 ERCLK32K is not output. #00 01 ERCLK32K is output on PTB3. #01 OSC32KSEL 32K Oscillator Clock Select 18 2 read-write 00 32kHz oscillator (OSC32KCLK) #00 10 RTC_CLKIN #10 11 LPO 1kHz #11 SIM_MISCTL This bit controls the function of BLE_RF_ACTIVE on PTC1/PTC19 ALT7 20 1 read-write 0 Chip low power mode output to PAD #0 1 BLE active output to PAD #1 SOPT2 System Options Register 2 0x1004 32 read-write n 0x0 0x0 CLKOUTSEL CLKOUT select 5 3 read-write 000 OSCERCLK DIV2 #000 001 OSCERCLK DIV4 #001 010 Bus clock #010 011 LPO clock 1 kHz #011 100 MCGIRCLK #100 101 OSCERCLK DIV8 #101 110 OSCERCLK #110 LPUART0SRC LPUART0 Clock Source Select 26 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 LPUART1SRC LPUART1 Clock Source Select 28 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 TPMSRC TPM Clock Source Select 24 2 read-write 00 Clock disabled #00 01 MCGFLLCLK clock #01 10 OSCERCLK clock #10 11 MCGIRCLK clock #11 SOPT4 System Options Register 4 0x100C 32 read-write n 0x0 0x0 TPM0CLKSEL TPM0 External Clock Pin Select 24 1 read-write 0 TPM0 external clock driven by TPM_CLKIN0 pin. #0 1 TPM0 external clock driven by TPM_CLKIN1 pin. #1 TPM1CH0SRC TPM1 Channel 0 Input Capture Source Select 18 1 read-write 0 TPM1_CH0 signal #0 1 CMP0 output #1 TPM1CLKSEL TPM1 External Clock Pin Select 25 1 read-write 0 TPM1 external clock driven by TPM_CLKIN0 pin. #0 1 TPM1 external clock driven by TPM_CLKIN1 pin. #1 TPM2CH0SRC TPM2 Channel 0 Input Capture Source Select 20 1 read-write 0 TPM2_CH0 signal #0 1 CMP0 output #1 TPM2CLKSEL TPM2 External Clock Pin Select 26 1 read-write 0 TPM2 external clock driven by TPM_CLKIN0 pin. #0 1 TPM2 external clock driven by TPM_CLKIN1 pin. #1 SOPT5 System Options Register 5 0x1010 32 read-write n 0x0 0x0 LPUART0ODE LPUART0 Open Drain Enable 16 1 read-write 0 Open drain is disabled on LPUART0. #0 1 Open drain is enabled on LPUART0. #1 LPUART0RXSRC LPUART0 Receive Data Source Select 2 1 read-write 0 LPUART_RX pin #0 1 CMP0 output #1 LPUART0TXSRC LPUART0 Transmit Data Source Select 0 2 read-write 00 LPUART0_TX pin #00 01 LPUART0_TX pin modulated with TPM1 channel 0 output #01 10 LPUART0_TX pin modulated with TPM2 channel 0 output #10 LPUART1ODE LPUART1 Open Drain Enable 17 1 read-write 0 Open drain is disabled on LPUART1. #0 1 Open drain is enabled on LPUART1 #1 LPUART1RXSRC LPUART1 Receive Data Source Select 6 1 read-write 0 LPUART1_RX pin #0 1 CMP0 output #1 LPUART1TXSRC LPUART1 Transmit Data Source Select 4 2 read-write 00 LPUART1_TX pin #00 01 LPUART1_TX pin modulated with TPM1 channel 0 output #01 10 LPUART1_TX pin modulated with TPM2 channel 0 output #10 SOPT7 System Options Register 7 0x1018 32 read-write n 0x0 0x0 ADC0ALTTRGEN ADC0 Alternate Trigger Enable 7 1 read-write 0 ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register. #0 1 ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion. #1 ADC0PRETRGSEL ADC0 Pretrigger Select 4 1 read-write 0 Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion and store the result in ADC0_RA register. #0 1 Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register. #1 ADC0TRGSEL ADC0 Trigger Select 0 4 read-write 0000 External trigger pin input (EXTRG_IN) #0000 0001 CMP0 output #0001 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 1000 TPM0 overflow #1000 1001 TPM1 overflow #1001 1010 TPM2 overflow #1010 1100 RTC alarm interrupt and RTC seconds interrupt #1100 1101 RTC seconds #1101 1110 LPTMR0 trigger #1110 1111 Radio TSM #1111 SRVCOP Service COP 0x1104 32 write-only n 0x0 0x0 SRVCOP Service COP Register 0 8 write-only UIDL Unique Identification Register Low 0x1060 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only n 0x0 0x0 UID Unique Identification 0 16 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only SMC System Mode Controller SMC 0x0 0x0 0x4 registers n PMCTRL Power Mode Control register 0x1 8 read-write n 0x0 0x0 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successful. #0 1 The previous stop mode entry was aborted. #1 STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 011 Low-Leakage Stop (LLSx) #011 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 PMPROT Power Mode Protection register 0x0 8 read-write n 0x0 0x0 ALLS Allow Low-Leakage Stop Mode 3 1 read-write 0 Any LLSx mode is not allowed #0 1 Any LLSx mode is allowed #1 AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 PMSTAT Power Mode Status register 0x3 8 read-only n 0x0 0x0 PMSTAT Power Mode Status 0 8 read-only STOPCTRL Stop Control Register 0x2 8 read-write n 0x0 0x0 LLSM LLS or VLLS Mode Control 0 3 read-write 000 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #000 001 VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #001 010 VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx #010 011 VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx #011 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 RAM2PO RAM2 Power Option 4 1 read-write 0 RAM2 not powered in LLS2/VLLS2 #0 1 RAM2 powered in LLS2/VLLS2 #1 SPI0 Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI0 10 CTAR0 Clock and Transfer Attributes Register (In Master Mode) SPI0 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 Clock and Transfer Attributes Register (In Master Mode) SPI0 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF Clear RX FIFO 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS0 Peripheral Chip Select x Inactive State 16 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 PCSIS1 Peripheral Chip Select x Inactive State 17 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 PCSIS2 Peripheral Chip Select x Inactive State 18 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 PCSIS3 Peripheral Chip Select x Inactive State 19 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 POPR POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS0 Select which PCS signals are to be asserted for the transfer 16 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 PCS1 Select which PCS signals are to be asserted for the transfer 17 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 PCS2 Select which PCS signals are to be asserted for the transfer 18 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 PCS3 Select which PCS signals are to be asserted for the transfer 19 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 16 read-write RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-only 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCR Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SPI1 Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI1 29 CTAR0 Clock and Transfer Attributes Register (In Master Mode) SPI1 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 Clock and Transfer Attributes Register (In Master Mode) SPI1 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI1 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF Clear RX FIFO 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS0 Peripheral Chip Select x Inactive State 16 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 PCSIS1 Peripheral Chip Select x Inactive State 17 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 PCSIS2 Peripheral Chip Select x Inactive State 18 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 PCSIS3 Peripheral Chip Select x Inactive State 19 1 read-write 0 The inactive state of PCSx is low. #0000 1 The inactive state of PCSx is high. #0001 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 POPR POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR PUSH TX FIFO Register In Master Mode SPI1 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS0 Select which PCS signals are to be asserted for the transfer 16 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 PCS1 Select which PCS signals are to be asserted for the transfer 17 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 PCS2 Select which PCS signals are to be asserted for the transfer 18 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 PCS3 Select which PCS signals are to be asserted for the transfer 19 1 read-write 0 Negate the PCS[x] signal #0000 1 Assert the PCS[x] signal. #0001 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI1 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 16 read-write RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-only 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCR Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TPM0 Timer/PWM Module TPM 0x0 0x0 0x88 registers n TPM0 17 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C2SC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C3SC Channel (n) Status and Control 0x6C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TPM1 Timer/PWM Module TPM 0x0 0x0 0x88 registers n TPM1 18 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TPM2 Timer/PWM Module TPM 0x0 0x0 0x88 registers n TPM2 19 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSEL Trigger Select 24 4 read-write 0001 Channel 0 pin input capture #0001 0010 Channel 1 pin input capture #0010 0011 Channel 0 or Channel 1 pin input capture #0011 0100 Channel 2 pin input capture #0100 0101 Channel 0 or Channel 2 pin input capture #0101 0110 Channel 1 or Channel 2 pin input capture #0110 0111 Channel 0 or Channel 1 or Channel 2 pin input capture #0111 1000 Channel 3 pin input capture #1000 1001 Channel 0 or Channel 3 pin input capture #1001 1010 Channel 1 or Channel 3 pin input capture #1010 1011 Channel 0 or Channel 1 or Channel 3 pin input capture #1011 1100 Channel 2 or Channel 3 pin input capture #1100 1101 Channel 0 or Channel 2 or Channel 3 pin input capture #1101 1110 Channel 1 or Channel 2 or Channel 3 pin input capture #1110 1111 Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture #1111 TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TRNG0 TRNG0 TRNG0 0x0 0x0 0xF8 registers n TRNG0 13 ENT0 Entropy Read Register 0x40 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT1 Entropy Read Register 0x44 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT10 Entropy Read Register 0x68 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT11 Entropy Read Register 0x6C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT12 Entropy Read Register 0x70 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT13 Entropy Read Register 0x74 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT14 Entropy Read Register 0x78 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT15 Entropy Read Register 0x7C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT2 Entropy Read Register 0x48 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT3 Entropy Read Register 0x4C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT4 Entropy Read Register 0x50 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT5 Entropy Read Register 0x54 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT6 Entropy Read Register 0x58 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT7 Entropy Read Register 0x5C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT8 Entropy Read Register 0x60 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT9 Entropy Read Register 0x64 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only FRQCNT Frequency Count Register TRNG0 0x1C 32 read-only n 0x0 0x0 FRQ_CT Frequency Count 0 22 read-only FRQMAX Frequency Count Maximum Limit Register TRNG0 0x1C 32 read-write n 0x0 0x0 FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write FRQMIN Frequency Count Minimum Limit Register 0x18 32 read-write n 0x0 0x0 FRQ_MIN Frequency Count Minimum Limit 0 22 read-write INT_CTRL Interrupt Control Register 0xB4 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding bit of INT_STATUS cleared. #0 1 Corresponding bit of INT_STATUS active. #1 UNUSED Reserved but writeable. 3 29 read-write INT_MASK Mask Register 0xB8 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding interrupt of INT_STATUS is masked. #0 1 Corresponding bit of INT_STATUS is active. #1 INT_STATUS Interrupt Status Register 0xBC 32 read-only n 0x0 0x0 ENT_VAL Read only: Entropy Valid 1 1 read-only 0 Busy generation entropy. Any value read is invalid. #0 1 TRNG can be stopped and entropy is valid if read. #1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-only 0 No hardware nor self test frequency errors. #0 1 The frequency counter has detected a failure. #1 HW_ERR Read: Error status 0 1 read-only 0 no error #0 1 error detected. #1 MCTL Miscellaneous Control Register 0x0 32 read-write n 0x0 0x0 ENT_VAL Read only: Entropy Valid 10 1 read-only ERR Read: Error status 12 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only FOR_SCLK Force System Clock 7 1 read-write OSC_DIV Oscillator Divide 2 2 read-write 00 use ring oscillator with no divide #00 01 use ring oscillator divided-by-2 #01 10 use ring oscillator divided-by-4 #10 11 use ring oscillator divided-by-8 #11 PRGM Programming Mode Select 16 1 read-write RST_DEF Reset Defaults 6 1 write-only SAMP_MODE Sample Mode 0 2 read-write 00 use Von Neumann data into both Entropy shifter and Statistical Checker #00 01 use raw data into both Entropy shifter and Statistical Checker #01 10 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker #10 11 undefined/reserved. #11 TRNG_ACC TRNG Access Mode 5 1 read-write TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only UNUSED4 This bit is unused. Always reads zero. 4 1 read-only PKRCNT10 Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only n 0x0 0x0 PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only PKRCNT32 Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only n 0x0 0x0 PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only PKRCNT54 Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only n 0x0 0x0 PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only PKRCNT76 Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only n 0x0 0x0 PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only PKRCNT98 Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only n 0x0 0x0 PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only PKRCNTBA Statistical Check Poker Count B and A Register 0x94 32 read-only n 0x0 0x0 PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only PKRCNTDC Statistical Check Poker Count D and C Register 0x98 32 read-only n 0x0 0x0 PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only PKRCNTFE Statistical Check Poker Count F and E Register 0x9C 32 read-only n 0x0 0x0 PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only PKRMAX Poker Maximum Limit Register TRNG0 0xC 32 read-write n 0x0 0x0 PKR_MAX Poker Maximum Limit. 0 24 read-write PKRRNG Poker Range Register 0x8 32 read-write n 0x0 0x0 PKR_RNG Poker Range 0 16 read-write PKRSQ Poker Square Calculation Result Register TRNG0 0xC 32 read-only n 0x0 0x0 PKR_SQ Poker Square Calculation Result. 0 24 read-only SBLIM Sparse Bit Limit Register TRNG0 0x14 32 read-write n 0x0 0x0 SB_LIM Sparse Bit Limit 0 10 read-write SCMC Statistical Check Monobit Count Register TRNG0 0x20 32 read-only n 0x0 0x0 MONO_CT Monobit Count 0 16 read-only SCMISC Statistical Check Miscellaneous Register 0x4 32 read-write n 0x0 0x0 LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write SCML Statistical Check Monobit Limit Register TRNG0 0x20 32 read-write n 0x0 0x0 MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write SCR1C Statistical Check Run Length 1 Count Register TRNG0 0x24 32 read-only n 0x0 0x0 R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only SCR1L Statistical Check Run Length 1 Limit Register TRNG0 0x24 32 read-write n 0x0 0x0 RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write SCR2C Statistical Check Run Length 2 Count Register TRNG0 0x28 32 read-only n 0x0 0x0 R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only SCR2L Statistical Check Run Length 2 Limit Register TRNG0 0x28 32 read-write n 0x0 0x0 RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write SCR3C Statistical Check Run Length 3 Count Register TRNG0 0x2C 32 read-only n 0x0 0x0 R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only SCR3L Statistical Check Run Length 3 Limit Register TRNG0 0x2C 32 read-write n 0x0 0x0 RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write SCR4C Statistical Check Run Length 4 Count Register TRNG0 0x30 32 read-only n 0x0 0x0 R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only SCR4L Statistical Check Run Length 4 Limit Register TRNG0 0x30 32 read-write n 0x0 0x0 RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write SCR5C Statistical Check Run Length 5 Count Register TRNG0 0x34 32 read-only n 0x0 0x0 R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only SCR5L Statistical Check Run Length 5 Limit Register TRNG0 0x34 32 read-write n 0x0 0x0 RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write SCR6PC Statistical Check Run Length 6+ Count Register TRNG0 0x38 32 read-only n 0x0 0x0 R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only SCR6PL Statistical Check Run Length 6+ Limit Register TRNG0 0x38 32 read-write n 0x0 0x0 RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write SDCTL Seed Control Register 0x10 32 read-write n 0x0 0x0 ENT_DLY Entropy Delay 16 16 read-write SAMP_SIZE Sample Size 0 16 read-write SEC_CFG Security Configuration Register 0xB0 32 read-write n 0x0 0x0 NO_PRGM If set, the TRNG registers cannot be programmed 1 1 read-write 0 Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. #0 1 Overides Miscellaneous Control Register access mode and prevents TRNG register programming. #1 SH0 Reserved. DRNG specific, not applicable to this version. 0 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 SK_VAL Reserved. DRNG-specific, not applicable to this version. 2 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 STATUS Status Register 0x3C 32 read-only n 0x0 0x0 RETRY_CT RETRY COUNT 16 4 read-only TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TOTSAM Total Samples Register TRNG0 0x14 32 read-only n 0x0 0x0 TOT_SAM Total Samples 0 20 read-only VID1 Version ID Register (MS) 0xF0 32 read-only n 0x0 0x0 IP_ID Shows the IP ID. 16 16 read-only 0x0030 ID for TRNG. #110000 MAJ_REV Shows the IP's Major revision of the TRNG. 8 8 read-only 0x01 Major revision number for TRNG. #1 MIN_REV Shows the IP's Minor revision of the TRNG. 0 8 read-only 0x00 Minor revision number for TRNG. #0 VID2 Version ID Register (LS) 0xF4 32 read-only n 0x0 0x0 CONFIG_OPT Shows the IP's Configuaration options for the TRNG. 0 8 read-only 0x00 TRNG_CONFIG_OPT for TRNG. #0 ECO_REV Shows the IP's ECO revision of the TRNG. 8 8 read-only 0x00 TRNG_ECO_REV for TRNG. #0 ERA Shows the compile options for the TRNG. 24 8 read-only 0x00 COMPILE_OPT for TRNG. #0 INTG_OPT Shows the integration options for the TRNG. 16 8 read-only 0x00 INTG_OPT for TRNG. #0 VREF Voltage Reference VREF 0x0 0x0 0x2 registers n SC VREF Status and Control Register 0x1 8 read-write n 0x0 0x0 ICOMPEN Second order curvature compensation enable 5 1 read-write 0 Disabled #0 1 Enabled #1 MODE_LV Buffer Mode selection 0 2 read-write 00 Bandgap on only, for stabilization and startup #00 01 High power buffer mode enabled #01 10 Low-power buffer mode enabled #10 REGEN Regulator enable 6 1 read-write 0 Internal 1.75 V regulator is disabled. #0 1 Internal 1.75 V regulator is enabled. #1 VREFEN Internal Voltage Reference enable 7 1 read-write 0 The module is disabled. #0 1 The module is enabled. #1 VREFST Internal Voltage Reference stable 2 1 read-only 0 The module is disabled or not stable. #0 1 The module is stable. #1 TRM VREF Trim Register 0x0 8 read-write n 0x0 0x0 CHOPEN Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized. 6 1 read-write 0 Chop oscillator is disabled. #0 1 Chop oscillator is enabled. #1 TRIM Trim bits 0 6 read-write 000000 Min #0 111111 Max #111111 XCVR_ANALOG XCVR_ANALOG XCVR_ANALOG 0x0 0x0 0x3C registers n BALUN_RX RF Analog Balun RX Mode Control 0x2C 32 read-write n 0x0 0x0 RXTX_BAL_RX_CODE Balun Tuning Cap Settings in Receive Mode 0 24 read-write BALUN_TX RF Analog Balun TX Mode Control 0x28 32 read-write n 0x0 0x0 RXTX_BAL_TX_CODE Balun Tuning Cap Settings in Transmit Mode 0 24 read-write BB_LDO_1 RF Analog Baseband LDO Control 1 0x0 32 read-write n 0x0 0x0 BB_LDO_ADCDAC_BYP rmap_bb_ldo_adcdac_byp 0 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_ADCDAC_DIAGSEL rmap_bb_ldo_adcdac_diagsel 1 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_ADCDAC_SPARE rmap_bb_ldo_adcdac_spare[1:0] 2 2 read-write BB_LDO_ADCDAC_TRIM rmap_bb_ldo_adcdac_trim[2:0] 4 3 read-write 000 1.20 V ( Default ) #000 001 1.25 V #001 010 1.28 V #010 011 1.33 V #011 100 1.40 V #100 101 1.44 V #101 110 1.50 V #110 111 1.66 V #111 BB_LDO_BBA_BYP rmap_bb_ldo_bba_byp 8 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_BBA_DIAGSEL rmap_bb_ldo_bba_diagsel 9 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_BBA_SPARE rmap_bb_ldo_bba_spare[1:0] 10 2 read-write BB_LDO_BBA_TRIM rmap_bb_ldo_bba_trim[2:0] 12 3 read-write 0 1.20 V ( Default ) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_LDO_FDBK_BYP rmap_bb_ldo_fdbk_byp 16 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_FDBK_DIAGSEL rmap_bb_ldo_fdbk_diagsel 17 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_FDBK_SPARE rmap_bb_ldo_fdbk_spare[1:0] 18 2 read-write BB_LDO_FDBK_TRIM rmap_bb_ldo_fdbk_trim[2:0] 20 3 read-write 0 1.2/1.176 V ( Default ) #000 1 1.138/1.115 V #001 2 1.085/1.066 V #010 3 1.04/1.025 V #011 4 1.28/1.25 V #100 5 1.4/1.35 V #101 6 1.55/1.4 V #110 7 1.78/1.4 V #111 BB_LDO_HF_BYP rmap_bb_ldo_hf_byp 24 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_HF_DIAGSEL rmap_bb_ldo_hf_diagsel 25 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_HF_SPARE rmap_bb_ldo_hf_spare[1:0] 26 2 read-write BB_LDO_HF_TRIM rmap_bb_ldo_hf_trim[2:0] 28 3 read-write 0 1.20 V ( Default ) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_LDO_2 RF Analog Baseband LDO Control 2 0x4 32 read-write n 0x0 0x0 BB_LDO_PD_BYP rmap_bb_ldo_pd_byp 0 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_PD_DIAGSEL rmap_bb_ldo_pd_diagsel 1 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_PD_SPARE rmap_bb_ldo_pd_spare[1:0] 2 2 read-write BB_LDO_PD_TRIM rmap_bb_ldo_pd_trim[2:0] 4 3 read-write 0 1.20 V ( Default ) #000 1 1.25 V #001 2 1.28 V #010 3 1.33 V #011 4 1.40 V #100 5 1.44 V #101 6 1.50 V #110 7 1.66 V #111 BB_LDO_VCOLO_BYP rmap_bb_ldo_vcolo_byp 10 1 read-write 0 Bypass disabled. #0 1 Bypass enabled #1 BB_LDO_VCOLO_DIAGSEL rmap_bb_ldo_vcolo_diagsel 11 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_VCOLO_TRIM rmap_bb_ldo_vcolo_trim[2:0] 12 3 read-write 0 1.138/1.117 V ( Default ) #000 1 1.076/1.058 V #001 2 1.027/1.012 V #010 3 0.98/0.97 V #011 4 1.22/1.19 V #100 5 1.33/1.3 V #101 6 1.5/1.4 V #110 7 1.82/1.4 V #111 BB_LDO_VCO_SPARE rmap_bb_ldo_vco_spare[1:0] 8 2 read-write BB_LDO_VTREF_DIAGSEL rmap_bb_ldo_vtref_diagsel 16 1 read-write 0 Diag disable #0 1 Diag enable #1 BB_LDO_VTREF_TC rmap_bb_ldo_vtref_tc[1:0] 17 2 read-write 0 1.117/1.176 V #00 1 1.134/1.188 V #01 2 1.10/1.162 V #10 3 1.09/1.152 V #11 DFT_OBSV_1 RF Analog DFT Observation Register 1 0x30 32 read-only n 0x0 0x0 CTUNE_MAX_DIFF Maximum Frequency Count Difference found by the Coarse Tune BIST 20 12 read-only DFT_FREQ_COUNTER VCO Frequency Counter Value 0 19 read-only DFT_OBSV_2 RF Analog DFT Observation Register 2 0x34 32 read-write n 0x0 0x0 SYN_BIST_IGNORE_FAILS PLL Frequency Synthesizer BIST Ignore Fails 31 1 read-write SYN_BIST_MAX_DIFF PLL Frequency Synthesizer BIST Worst Frequency Count 0 17 read-only SYN_BIST_MAX_DIFF_CH PLL Frequency Synthesizer BIST Worst Channel 24 7 read-only DFT_OBSV_3 RF Analog DFT Observation Register 3 0x38 32 read-write n 0x0 0x0 HPM_BIST_INCREMENT HPM BIST Increment Value 0 3 read-write HPM_BIST_START HPM BIST Start Value 16 8 read-write HPM_BIST_STOP HPM BIST Stop Value 8 8 read-write RX_ADC RF Analog ADC Control 0x8 32 read-write n 0x0 0x0 RX_ADC_BUMP rmap_rx_adc_bump[7:0] 0 8 read-write RX_ADC_FS_SEL rmap_rx_adc_fs_sel[1:0] 8 2 read-write 0 52MHz (2x26MHz) #00 1 64MHz (2x32MHz) #01 2 +13% of 64MHz #10 3 - 11% of 64MHz #11 RX_ADC_I_DIAGSEL rmap_rx_adc_i_diagsel 10 1 read-write RX_ADC_Q_DIAGSEL rmap_rx_adc_q_diagsel 11 1 read-write RX_ADC_SPARE rmap_rx_adc_spare[3:0] 12 4 read-write RX_AUXPLL RF Analog Aux PLL Control 0x18 32 read-write n 0x0 0x0 BIAS_TRIM rmap_rxtx_auxpll_bias_trim[2:0] 0 3 read-write DIAGSEL1 rmap_rxtx_auxpll_diagsel1 3 1 read-write DIAGSEL2 rmap_rxtx_auxpll_diagsel2 4 1 read-write LF_CNTL rmap_rxtx_auxpll_lf_cntl[2:0] 5 3 read-write RXTX_BAL_BIAST rmap_rxtx_bal_biast[1:0] 20 2 read-write 0 0.6 #00 1 0.4 #01 2 0.9 #10 3 1.2 #11 RXTX_BAL_SPARE rmap_rxtx_bal_spare[2:0] 24 3 read-write RXTX_RCCAL_DIAGSEL rmap_rxtx_rccal_diagsel 28 1 read-write SPARE rmap_rxtx_auxpll_spare[3:0] 8 4 read-write VCO_DAC_REF_ADJUST rmap_rxtx_auxpll_vco_dac_ref_adjust[3:0] 12 4 read-write VTUNE_TESTMODE rmap_rxtx_auxpll_vtune_testmode 16 1 read-write RX_BBA RF Analog BBA Control 0xC 32 read-write n 0x0 0x0 RX_BBA2_BW_SEL rmap_bba2_bw_sel[2:0] 24 3 read-write 000 1000K #000 001 900K #001 010 800K #010 011 700K Default #011 100 600K #100 101 500K #101 RX_BBA2_SPARE rmap_rx_bba2_spare[2:0] 28 3 read-write RX_BBA_BW_SEL rmap_rx_bba_bw_sel[2:0] 0 3 read-write 000 1000K #000 001 900K #001 010 800K #010 011 700K Default #011 100 600K #100 101 500K #101 RX_BBA_CUR_BUMP rmap_rx_bba_cur_bump 3 1 read-write RX_BBA_DIAGSEL1 rmap_rx_bba_diagsel1 4 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_DIAGSEL2 rmap_rx_bba_diagsel2 5 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_DIAGSEL3 rmap_rx_bba_diagsel3 6 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_DIAGSEL4 rmap_rx_bba_diagsel4 7 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_BBA_SPARE rmap_rx_bba_spare[5:0] 16 6 read-write 00 600mV (Default) #0 01 675mV #1 10 450mV #10 11 525mV #11 RX_LNA RF Analog LNA Control 0x10 32 read-write n 0x0 0x0 RX_LNA_BUMP rmap_rx_lna_bump[3:0] 0 4 read-write 0 Default #0000 1 -25% #0001 2 +50% #0010 3 +25% #0011 4 CM 480mV #0100 8 CM 600mV #1000 12 CM 660mV #1100 RX_LNA_HG_DIAGSEL rmap_rx_lna_hg_diagsel 4 1 read-write RX_LNA_HIZ_ENABLE rmap_rx_lna_hiZ_enable 5 1 read-write RX_LNA_LG_DIAGSEL rmap_rx_lna_lg_diagsel 6 1 read-write RX_LNA_SPARE rmap_rx_lna_spare[1:0] 8 2 read-write RX_MIXER_BUMP rmap_rx_mixer_bump[3:0] 16 4 read-write 0 825mV (Default) #0000 1 750mV #0001 2 900mV #0010 3 975mV #0011 RX_MIXER_SPARE rmap_rx_mixer_spare 20 1 read-write RX_TZA RF Analog TZA Control 0x14 32 read-write n 0x0 0x0 RX_TZA1_DIAGSEL rmap_rx_tza1_diagsel 24 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_TZA2_DIAGSEL rmap_rx_tza2_diagsel 25 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_TZA3_DIAGSEL rmap_rx_tza3_diagsel 26 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_TZA4_DIAGSEL rmap_rx_tza4_diagsel 27 1 read-write 0 Diag disable #0 1 Diag enable #1 RX_TZA_BW_SEL rmap_rx_tza_bw_sel[2:0] 0 3 read-write 000 1000K #000 001 900K #001 010 800K #010 011 700K Default #011 100 600K #100 101 500K #101 RX_TZA_CUR_BUMP rmap_rx_tza_cur_bump 3 1 read-write RX_TZA_GAIN_BUMP rmap_rx_tza_gain_bump 4 1 read-write RX_TZA_SPARE rmap_rx_tza_spare[5:0] 16 6 read-write 00 600mV (Default) #0 01 675mV #1 10 450mV #10 11 525mV #11 SY_CTRL_1 RF Analog Synthesizer Control 1 0x1C 32 read-write n 0x0 0x0 SY_DIVN_SPARE rmap_sy_divn_spare 0 1 read-write SY_FCAL_SPARE rmap_sy_fcal_spare 1 1 read-write SY_LO_BUMP_RTLO_FDBK rmap_sy_lo_bump_rtlo_fdbk[1:0] 4 2 read-write 0 1.045 V #00 1 1.084 V #01 2 1.097 V #10 3 1.10 V #11 SY_LO_BUMP_RTLO_RX rmap_sy_lo_bump_rtlo_rx[1:0] 6 2 read-write 0 1.051/1.037 V #00 1 1.082/1.075 V #01 2 1.092/1.088 V #10 3 1.098/1.094 V #11 SY_LO_BUMP_RTLO_TX rmap_sy_lo_bump_rtlo_tx[1:0] 8 2 read-write 0 1.071/1.065 V #00 1 1.092/1.090 V #01 2 1.099/1.098 V #10 3 1.10/1.1 V #11 SY_LO_DIAGSEL rmap_sy_lo_diagsel 10 1 read-write 0 Diag disable #0 1 Diag enable #1 SY_LO_SPARE rmap_sy_lo_spare[2:0] 12 3 read-write SY_LPF_FILT_CTRL rmap_sy_lpf_filt_ctrl[2:0] 16 3 read-write SY_LPF_SPARE rmap_sy_lpf_spare 19 1 read-write SY_PD_DIAGSEL rmap_sy_pd_diagsel 20 1 read-write SY_PD_PCH_SEL rmap_sy_pd_pch_sel 23 1 read-write 0 inverter based precharge #0 1 resistor divider based precharge #1 SY_PD_PCH_TUNE rmap_sy_pd_pch_tune[1:0] 21 2 read-write SY_PD_SPARE rmap_sy_pd_spare[1:0] 24 2 read-write 0 Default #00 1 PD output is pulled down. #01 SY_PD_VTUNE_OVERRIDE_TEST_MODE rmap_sy_pd_vtune_override_test_mode 28 1 read-write SY_CTRL_2 RF Analog Synthesizer Control 2 0x20 32 read-write n 0x0 0x0 SY_VCO_BIAS rmap_sy_vco_bias[2:0] 0 3 read-write 0 0.97V #000 1 1.033V #001 2 1.06V #010 3 1.07V #011 4 1.08V #100 5 1.085V #101 6 1.090V #110 7 1.095V #111 SY_VCO_DIAGSEL rmap_sy_vco_diagsel 3 1 read-write 0 Diag disable #0 1 Diag enable #1 SY_VCO_KV rmap_sy_vco_kv[2:0] 4 3 read-write 0 50MHz/V #000 1 60MHz/V #001 2 70MHz/V #010 3 80MHz/V #011 4 80MHz/V #100 5 80MHz/V #101 6 80MHz/V #110 7 80MHz/V #111 SY_VCO_KVM rmap_sy_vco_kvm[2:0] 8 3 read-write 0 10MHz/V #000 1 20MHz/V #001 2 30MHz/V #010 3 40MHz/V #011 4 40MHz/V #100 5 40MHz/V #101 6 40MHz/V #110 7 40MHz/V #111 SY_VCO_PK_DET_ON rmap_sy_vco_pk_det_on 12 1 read-write 0 Disable #0 1 Enable #1 SY_VCO_SPARE rmap_sy_vco_spare[2:0] 14 3 read-write TX_DAC_PA RF Analog TX HPM DAC and PA Control 0x24 32 read-write n 0x0 0x0 TX_DAC_BUMP_CAP rmap_tx_dac_bump_cap[1:0] 0 2 read-write 0 1pF(default) #00 1 1.5pF #01 2 1.5pF #10 3 2pF #11 TX_DAC_BUMP_IDAC rmap_tx_dac_bump_idac[1:0] 3 2 read-write 0 250nA(default) #00 1 207nA #01 2 312nA #10 3 415nA #11 TX_DAC_BUMP_RLOAD rmap_tx_dac_bump_rload[1:0] 6 2 read-write 0 3.12 kohms(default) #00 1 2.34 kohms #01 2 3.9 kohms #10 3 4.6 kohms #11 TX_DAC_DIAGSEL rmap_tx_dac_diagsel 9 1 read-write 0 Disable Diag #0 1 Enable Diag #1 TX_DAC_INVERT_CLK rmap_tx_dac_invert_clk 10 1 read-write TX_DAC_OPAMP_DIAGSEL rmap_tx_dac_opamp_diagsel 11 1 read-write 0 Disable Diag #0 1 Enable Diag #1 TX_DAC_SPARE rmap_tx_dac_spare[2:0] 13 3 read-write TX_PA_BUMP_VBIAS rmap_tx_pa_bump_vbias[2:0] 17 3 read-write 0 0.557 #000 1 0.651 #001 2 0.741 #010 3 0.822 #011 4 0.590 #100 5 0.683 #101 6 0.771 #110 7 0.850 #111 TX_PA_DIAGSEL rmap_tx_pa_diagsel 21 1 read-write TX_PA_SPARE rmap_tx_pa_spare[2:0] 23 3 read-write XCVR_MISC XCVR_MISC XCVR_MISC 0x0 0x0 0x40 registers n BLE_ARB_CTRL BLE ARBITRATION CONTROL 0x8 32 read-write n 0x0 0x0 BLE_RELINQUISH BLE Relinquish Control 0 1 read-write XCVR_BUSY Transceiver Busy Status Bit 1 1 read-only 0 RF Channel in available (TSM is idle) #0 1 RF Channel in use (TSM is busy) #1 COEX_CTRL COEXISTENCE CONTROL 0x2C 32 read-write n 0x0 0x0 RF_NOT_ALLOWED RF_NOT_ALLOWED 9 1 read-only RF_NOT_ALLOWED_ASSERTED RF_NOT_ALLOWED_ASSERTED 6 1 read-write 0 Assertion on RF_NOT_ALLOWED has not occurred #0 1 Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared #1 RF_NOT_ALLOWED_EN RF_NOT_ALLOWED PER-LINK-LAYER ENABLE 0 4 read-write RF_NOT_ALLOWED_NO_RX RF_NOT_ALLOWED_NO_RX 5 1 read-write 0 Assertion on RF_NOT_ALLOWED has no effect on RX #0 1 Assertion on RF_NOT_ALLOWED can abort RX #1 RF_NOT_ALLOWED_NO_TX RF_NOT_ALLOWED_NO_TX 4 1 read-write 0 Assertion on RF_NOT_ALLOWED has no effect on TX #0 1 Assertion on RF_NOT_ALLOWED can abort TX #1 RF_NOT_ALLOWED_RX_ABORT RF_NOT_ALLOWED_RX_ABORT 8 1 read-write 0 A RX abort due to assertion on RF_NOT_ALLOWED has not occurred #0 1 A RX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared #1 RF_NOT_ALLOWED_TX_ABORT RF_NOT_ALLOWED_TX_ABORT 7 1 read-write 0 A TX abort due to assertion on RF_NOT_ALLOWED has not occurred #0 1 A TX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared #1 TSM_SPARE1_EXTEND TSM_SPARE1_EX Extension Duration 16 8 read-write CRCW_CFG CRC/WHITENER CONFIG REGISTER 0x30 32 read-write n 0x0 0x0 CRCW_EC_EN CRC Error Correction Enable 1 1 read-write CRCW_EN CRC calculation enable 0 1 read-write CRC_EARLY_FAIL CRC error correction fail 3 1 read-only CRC_EC_DONE CRC error correction done 28 1 read-only CRC_EC_FAIL CRC error correction fail 29 1 read-only CRC_EC_OFFSET CRC error correction offset 16 11 read-only CRC_RES_OUT_VLD CRC result output valid 4 1 read-only CRC_ZERO CRC zero 2 1 read-only CRCW_CFG2 CRC/WHITENER CONFIG 2 REGISTER 0x3C 32 read-write n 0x0 0x0 CRC_EC_LPKT_WND Error correction long packet burst error window 12 4 read-write CRC_EC_SPKT_BYTES Error Correction Short Packet Bytes 0 8 read-write CRC_EC_SPKT_WND Error correction short packet burst error window 8 4 read-write CRC_EC_MASK CRC ERROR CORRECTION MASK 0x34 32 read-only n 0x0 0x0 CRC_EC_MASK CRC error correction mask 0 32 read-only CRC_RES_OUT CRC RESULT 0x38 32 read-only n 0x0 0x0 CRC_RES_OUT CRC result output 0 32 read-only DMA_CTRL TRANSCEIVER DMA CONTROL 0x14 32 read-write n 0x0 0x0 BYPASS_DMA_SYNC Bypass External DMA Synchronization 5 1 read-write 0 Don't Bypass External Synchronization. Use this setting if SINGLE_REQ_MODE=1. #0 1 Bypass External Synchronization. This setting is mandatory if SINGLE_REQ_MODE=0. #1 DMA_AA_TRIGGERED DMA Access Address triggered 6 1 read-only DMA_EN DMA Enable 4 1 read-write DMA_PAGE Transceiver DMA Page Selector 0 4 read-write 0000 DMA Idle #0000 0001 RX_DIG I and Q #0001 0010 RX_DIG I Only #0010 0011 RX_DIG Q Only #0011 0100 RAW ADC I and Q #0100 0101 RAW ADC I Only #0101 0110 RAW ADC Q only #0110 0111 DC Estimator I and Q #0111 1000 DC Estimator I Only #1000 1001 DC Estimator Q only #1001 1010 RX_DIG Phase Output #1010 1100 Demodulator Soft Decision #1100 1101 Demodulator Data Output #1101 1110 Demodulator CFO Phase Output #1110 DMA_START_EDGE DMA Start Trigger Edge Selector 15 1 read-write 0 Trigger fires on a rising edge of the selected trigger source #0 1 Trigger fires on a falling edge of the selected trigger source #1 DMA_START_TRG DMA Start Trigger Selector 12 3 read-write DMA_START_TRIGGERED DMA Start Trigger Occurred 16 1 read-only DMA_TIMED_OUT DMA Transfer Timed Out 7 1 read-write 0 A DMA timeout has not occurred #0 1 A DMA timeout has occurred in Single Request Mode since the last time this bit was cleared #1 DMA_TIMEOUT DMA Timeout 8 4 read-write SINGLE_REQ_MODE DMA Single Request Mode 17 1 read-write 0 Disable Single Request Mode. The transceiver will assert ipd_req_radio_rx whenever it has a new sample ready for transfer. #0 1 Enable Single Request Mode. A single initial request by the transceiver will transfer the entire DMA block of data #1 DMA_DATA TRANSCEIVER DMA DATA 0x18 32 read-only n 0x0 0x0 DMA_DATA DMA Data Register 0 32 read-only FAD_CTRL FAD CONTROL 0x24 32 read-write n 0x0 0x0 ANTX This bit currently has no functionality 1 1 read-write ANTX_CTRLMODE Antenna Diversity Control Mode 7 1 read-write ANTX_EN These bits currently have no functionality 4 2 read-write ANTX_HZ This bit currently has no functionality 6 1 read-write ANTX_POL FAD Antenna Controls Polarity 8 4 read-write FAD_EN This bit currently has no functionality 0 1 read-write FAD_NOT_GPIO FAD versus GPIO Mode Selector 12 4 read-write OVERWRITE_VER OVERWRITE VERSION 0xC 32 read-write n 0x0 0x0 OVERWRITE_VER Overwrite Version Number. 0 8 read-write PACKET_RAM_CTRL PACKET RAM CONTROL 0x1C 32 read-write n 0x0 0x0 ALL_PROTOCOLS_ALLOW Allow IPS bus access to Packet RAM for any protocol at any time. 7 1 read-write 0 IPS bus access to Packet RAM is restricted to the protocol engine currently selected by XCVR_CTRL[PROTOCOL]. #0 1 All IPS bus access to Packet RAM permitted, regardless of XCVR_CTRL[PROTOCOL] setting #1 DBG_AA_TRIGGERED Packet Ram Debug Access Address triggered 10 1 read-only DBG_EN Packet RAM Debug Mode Enable 4 1 read-write DBG_PAGE Packet RAM Debug Page Selector 0 4 read-write 0000 Packet RAM Debug Mode Idle #0000 0001 RX_DIG I and Q #0001 0100 RAW ADC I and Q #0100 0111 DC Estimator I and Q #0111 1010 RX_DIG Phase Output #1010 1100 Demodulator Soft Decision #1100 1101 Demodulator Data Output #1101 1110 Demodulator CFO Phase Output #1110 DBG_RAM_FULL DBG_RAM_FULL[1:0] 8 2 read-only 00 Neither Packet RAM0 nor RAM1 is full #00 DBG_SOFT_INFO_SEL Packet RAM Debug PHY Soft Info Output Selector 11 1 read-write 0 PHY input cg_vbr_en is used to capture soft decision data #0 1 PHY output fsk_demod_bit_valid is used to capture soft decision data #1 DBG_START_EDGE Packet RAM Debug Start Trigger Edge Selector 15 1 read-write 0 Trigger fires on a rising edge of the selected trigger source #0 1 Trigger fires on a falling edge of the selected trigger source #1 DBG_START_TRG Packet RAM Debug Start Trigger Selector 12 3 read-write DBG_START_TRIGGERED Packet RAM Debug Start Triggered 21 1 read-only DBG_STOP_EDGE Packet RAM Debug Stop Trigger Edge Selector 20 1 read-write 0 Trigger fires on a rising edge of the selected trigger source #0 1 Trigger fires on a falling edge of the selected trigger source #1 DBG_STOP_TRG Packet RAM Debug Stop Trigger Selector 16 4 read-write DBG_STOP_TRIGGERED Packet RAM Debug Stop Triggered 22 1 read-only PB_PROTECT Packet Buffer Protect 23 1 read-write 0 Incoming received packets overwrite Packet Buffer RX contents (default) #0 1 Incoming received packets are blocked from overwriting Packet Buffer RX contents #1 RAM0_CE_ON_OVRD Override value for RAM0 CE (Chip Enable) 29 1 read-write RAM0_CE_ON_OVRD_EN Override control for RAM0 CE (Chip Enable) 28 1 read-write 0 Normal operation. #0 1 Use the state of RAM0_CE_ON_OVRD to override the RAM0 CE. #1 RAM0_CLK_ON_OVRD Override value for RAM0 Clock Gate Enable 25 1 read-write RAM0_CLK_ON_OVRD_EN Override control for RAM0 Clock Gate Enable 24 1 read-write 0 Normal operation. #0 1 Use the state of RAM0_CLK_ON_OVRD to override the RAM0 Clock Gate Enable. #1 RAM1_CE_ON_OVRD Override value for RAM1 CE (Chip Enable) 31 1 read-write RAM1_CE_ON_OVRD_EN Override control for RAM1 CE (Chip Enable) 30 1 read-write 0 Normal operation. #0 1 Use the state of RAM1_CE_ON_OVRD to override the RAM1 CE. #1 RAM1_CLK_ON_OVRD Override value for RAM1 Clock Gate Enable 27 1 read-write RAM1_CLK_ON_OVRD_EN Override control for RAM1 Clock Gate Enable 26 1 read-write 0 Normal operation. #0 1 Use the state of RAM1_CLK_ON_OVRD to override the RAM1 Clock Gate Enable. #1 XCVR_RAM_ALLOW Allow Packet RAM Transceiver Access 6 1 read-write 0 Protocol Engines, and associated IPS busses, have exclusive access to Packet RAM (mission mode) #0 1 Transceiver-space access to Packet RAM, including Packet RAM debug mode, are allowed #1 XCVR_RAM_PAGE RAM Page Selector for XCVR Access 5 1 read-write 0 RAM0 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF #0 1 RAM1 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF #1 RAM_STOP_ADDR PACKET RAM DEBUG RAM STOP ADDRESS 0x20 32 read-only n 0x0 0x0 RAM0_STOP_ADDR RAM0 Stop Address 0 11 read-only RAM1_STOP_ADDR RAM1 Stop Address 16 11 read-only XCVR_CTRL TRANSCEIVER CONTROL 0x0 32 read-write n 0x0 0x0 DEMOD_SEL Demodulator Selector 12 2 read-write 00 No demodulator selected #00 01 Use NXP Multi-standard PHY demodulator #01 PROTOCOL Radio Protocol Selection 0 4 read-write 0000 BLE #0000 0001 BLE in MBAN #0001 0010 BLE overlap MBAN #0010 0110 Radio Channels 0-127 selectable, FSK #0110 0111 Radio Channels 0-127 selectable, GFSK #0111 1000 Generic GFSK, with Gaussian Filter #1000 1001 Generic MSK, O-QPSK encoding #1001 1010 Generic FSK, direct +/- Fdev FSK #1010 RADIO0_IRQ_SEL RADIO0_IRQ_SEL 16 3 read-write 000 Assign Radio #0 Interrupt to BLE #000 001 Radio #0 Interrupt unassigned #001 010 Radio #0 Interrupt unassigned #010 011 Assign Radio #0 Interrupt to GENERIC_FSK #011 100 Radio #0 Interrupt unassigned #100 101 Radio #0 Interrupt unassigned #101 110 Radio #0 Interrupt unassigned #110 111 Radio #0 Interrupt unassigned #111 RADIO1_IRQ_SEL RADIO1_IRQ_SEL 20 3 read-write 000 Assign Radio #1 Interrupt to BLE #000 001 Radio #1 Interrupt unassigned #001 010 Radio #1 Interrupt unassigned #010 011 Assign Radio #1 Interrupt to GENERIC_FSK #011 100 Radio #1 Interrupt unassigned #100 101 Radio #1 Interrupt unassigned #101 110 Radio #1 Interrupt unassigned #110 111 Radio #1 Interrupt unassigned #111 REF_CLK_FREQ Radio Reference Clock Frequency 8 2 read-write 00 32 MHz #00 01 26 MHz #01 SOC_RF_OSC_CLK_GATE_EN SOC_RF_OSC_CLK_GATE_EN 11 1 read-write TGT_PWR_SRC Target Power Source 4 3 read-write TSM_LL_INHIBIT TSM Per-Link-Layer Inhibit 24 4 read-write XCVR_STATUS TRANSCEIVER STATUS 0x4 32 read-write n 0x0 0x0 BTLE_SYSCLK_REQ BTLE System Clock Request 16 1 read-only PLL_SEQ_STATE PLL Sequence State 8 4 read-only 0 PLL OFF #0000 2 CTUNE #0010 3 CTUNE_SETTLE #0011 6 HPMCAL1 #0110 8 HPMCAL1_SETTLE #1000 10 HPMCAL2 #1010 12 HPMCAL2_SETTLE #1100 15 PLLREADY #1111 RIF_LL_ACTIVE Link Layer Active Indication 17 1 read-only RX_MODE Receive Mode 12 1 read-only SOC_USING_RF_OSC_CLK SOC Using RF Clock Indication 19 1 read-only TSM_COUNT TSM_COUNT 0 8 read-only TSM_IRQ0 TSM Interrupt #0 24 1 read-write 0 TSM Interrupt #0 is not asserted. #0 1 TSM Interrupt #0 is asserted. Write '1' to this bit to clear it. #1 TSM_IRQ1 TSM Interrupt #1 25 1 read-write 0 TSM Interrupt #1 is not asserted. #0 1 TSM Interrupt #1 is asserted. Write '1' to this bit to clear it. #1 TX_MODE Transmit Mode 13 1 read-only XTAL_READY RF Osciallator Xtal Ready 18 1 read-only 0 Indicates that the RF Oscillator is disabled or has not completed its warmup. #0 1 Indicates that the RF Oscillator has completed its warmup count and is ready for use. #1 XCVR_PHY XCVR_PHY XCVR_PHY 0x0 0x0 0x30 registers n CFG1 PHY CONFIGURATION REGISTER 1 0x20 32 read-write n 0x0 0x0 AA_OUTPUT_SEL Access Address Output Select 2 1 read-write 0 demodulated #0 1 matched #1 AA_PLAYBACK Access Address Playback 1 1 read-write BLE_NTW_ADR_THR BLE Network Address Match Bit Error Threshold 28 3 read-write BSM_EN_BLE BLE Bit Streaming Mode Enable bit 5 1 read-write 0 BSM for BLE disabled #0 1 BSM for BLE enabled #1 CTS_THRESH CTS Correlation Threshold 8 8 read-write DEMOD_CLK_MODE Demodulator Clock Mode 6 2 read-write 0 Normal #00 1 Demodulate all samples #01 FSK_BIT_INVERT FSK Bit Invert 3 1 read-write FSK_FTS_TIMEOUT FSK FTS Timeout 20 3 read-write 0 4 symbols #000 1 5 symbols #001 2 6 symbols #010 3 7 symbols #011 4 8 symbols #100 5 9 symbols #101 6 10 symbols #110 7 11 symbols #111 RFU00 Reserved for future use. 4 1 read-write RFU01 Reserved for future use. 24 1 read-write RFU02 Reserved for future use. 25 1 read-write CFG2 PHY CONFIGURATION REGISTER 2 0x24 32 read-write n 0x0 0x0 PHY_CLK_ON Force PHY Clock On (testmode) 31 1 read-write 0 PHY clock is enabled by TSM output: rx_phy_en #0 1 PHY clock is forced on at all times #1 PHY_FIFO_PRECHG PHY FIFO Precharge Level 0 4 read-write RFU03 Reserved for future use. 4 1 read-write RFU04 Reserved for future use. 5 1 read-write RFU05 Reserved for future use. 6 1 read-write RFU06 Reserved for future use. 7 1 read-write RFU07 Reserved for future use. 16 1 read-write RFU08 Reserved for future use. 17 1 read-write RFU09 Reserved for future use. 18 1 read-write RFU10 Reserved for future use. 19 1 read-write RFU11 Reserved for future use. 20 1 read-write RFU12 Reserved for future use. 21 1 read-write RFU13 Reserved for future use. 22 1 read-write RFU14 Reserved for future use. 23 1 read-write RFU15 Reserved for future use. 24 1 read-write RFU16 Reserved for future use. 25 1 read-write X2_DEMOD_GAIN X2_DEMOD_GAIN 8 4 read-write EL_CFG PHY EARLY/LATE CONFIGURATION REGISTER 0x28 32 read-write n 0x0 0x0 EL_ENABLE EL_ENABLE 0 1 read-write 0 Disable Early/Late #0 1 Enable Early/Late #1 EL_INTERVAL EL_INTERVAL 16 6 read-write EL_WIN_SIZE EL_WIN_SIZE 8 4 read-write NTW_ADR_BSM PHY NETWORK ADDRESS FOR BSM 0x2C 32 read-write n 0x0 0x0 NTW_ADR_BSM NTW_ADR_BSM 0 32 read-write PRE_REF0 PREAMBLE REFERENCE WAVEFORM 0 0x0 32 read-write n 0x0 0x0 FSK_PREAMBLE_REF0 Base preamble reference waveform containing sixteen 5-bit phase values represented in 2's complement notation using 1 sign bit and 4 fractional bits 0 32 read-write PRE_REF1 PREAMBLE REFERENCE WAVEFORM 1 0x4 32 read-write n 0x0 0x0 FSK_PREAMBLE_REF1 Refer to FSK_PREAMBLE_REF0. 0 32 read-write PRE_REF2 PREAMBLE REFERENCE WAVEFORM 2 0x8 32 read-write n 0x0 0x0 FSK_PREAMBLE_REF2 Refer to FSK_PREAMBLE_REF0. 0 16 read-write STATUS PHY STATUS REGISTER 0x30 32 read-only n 0x0 0x0 AA_MATCHED Access Address Matched 4 4 read-only 0000 No Network Address has matched #0000 0001 Network Address 0 has matched #0001 0010 Network Address 1 has matched #0010 0100 Network Address 2 has matched #0100 1000 Network Address 3 has matched #1000 AA_SFD_MATCHED Access Address or SFD Found 1 1 read-only CFO_ESTIMATE Carrier Frequency Offset Estimate 16 8 read-only DATA_FIFO_DEPTH DATA FIFO DEPTH 12 4 read-only HAMMING_DISTANCE HAMMING DISTANCE 8 3 read-only PREAMBLE_FOUND Preamble Found 0 1 read-only XCVR_PKT_RAM XCVR_PKT_RAM XCVR_PKT_RAM 0x0 0x0 0x900 registers n PACKET_RAM_0 Shared Packet RAM for multiple Link Layer usage. 0x0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1 Shared Packet RAM for multiple Link Layer usage. 0x2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_10 Shared Packet RAM for multiple Link Layer usage. 0x14 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_100 Shared Packet RAM for multiple Link Layer usage. 0xC8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1000 Shared Packet RAM for multiple Link Layer usage. 0x7D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1001 Shared Packet RAM for multiple Link Layer usage. 0x7D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1002 Shared Packet RAM for multiple Link Layer usage. 0x7D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1003 Shared Packet RAM for multiple Link Layer usage. 0x7D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1004 Shared Packet RAM for multiple Link Layer usage. 0x7D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1005 Shared Packet RAM for multiple Link Layer usage. 0x7DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1006 Shared Packet RAM for multiple Link Layer usage. 0x7DC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1007 Shared Packet RAM for multiple Link Layer usage. 0x7DE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1008 Shared Packet RAM for multiple Link Layer usage. 0x7E0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1009 Shared Packet RAM for multiple Link Layer usage. 0x7E2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_101 Shared Packet RAM for multiple Link Layer usage. 0xCA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1010 Shared Packet RAM for multiple Link Layer usage. 0x7E4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1011 Shared Packet RAM for multiple Link Layer usage. 0x7E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1012 Shared Packet RAM for multiple Link Layer usage. 0x7E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1013 Shared Packet RAM for multiple Link Layer usage. 0x7EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1014 Shared Packet RAM for multiple Link Layer usage. 0x7EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1015 Shared Packet RAM for multiple Link Layer usage. 0x7EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1016 Shared Packet RAM for multiple Link Layer usage. 0x7F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1017 Shared Packet RAM for multiple Link Layer usage. 0x7F2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1018 Shared Packet RAM for multiple Link Layer usage. 0x7F4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1019 Shared Packet RAM for multiple Link Layer usage. 0x7F6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_102 Shared Packet RAM for multiple Link Layer usage. 0xCC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1020 Shared Packet RAM for multiple Link Layer usage. 0x7F8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1021 Shared Packet RAM for multiple Link Layer usage. 0x7FA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1022 Shared Packet RAM for multiple Link Layer usage. 0x7FC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1023 Shared Packet RAM for multiple Link Layer usage. 0x7FE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1024 Shared Packet RAM for multiple Link Layer usage. 0x800 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1025 Shared Packet RAM for multiple Link Layer usage. 0x802 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1026 Shared Packet RAM for multiple Link Layer usage. 0x804 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1027 Shared Packet RAM for multiple Link Layer usage. 0x806 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1028 Shared Packet RAM for multiple Link Layer usage. 0x808 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1029 Shared Packet RAM for multiple Link Layer usage. 0x80A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_103 Shared Packet RAM for multiple Link Layer usage. 0xCE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1030 Shared Packet RAM for multiple Link Layer usage. 0x80C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1031 Shared Packet RAM for multiple Link Layer usage. 0x80E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1032 Shared Packet RAM for multiple Link Layer usage. 0x810 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1033 Shared Packet RAM for multiple Link Layer usage. 0x812 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1034 Shared Packet RAM for multiple Link Layer usage. 0x814 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1035 Shared Packet RAM for multiple Link Layer usage. 0x816 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1036 Shared Packet RAM for multiple Link Layer usage. 0x818 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1037 Shared Packet RAM for multiple Link Layer usage. 0x81A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1038 Shared Packet RAM for multiple Link Layer usage. 0x81C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1039 Shared Packet RAM for multiple Link Layer usage. 0x81E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_104 Shared Packet RAM for multiple Link Layer usage. 0xD0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1040 Shared Packet RAM for multiple Link Layer usage. 0x820 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1041 Shared Packet RAM for multiple Link Layer usage. 0x822 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1042 Shared Packet RAM for multiple Link Layer usage. 0x824 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1043 Shared Packet RAM for multiple Link Layer usage. 0x826 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1044 Shared Packet RAM for multiple Link Layer usage. 0x828 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1045 Shared Packet RAM for multiple Link Layer usage. 0x82A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1046 Shared Packet RAM for multiple Link Layer usage. 0x82C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1047 Shared Packet RAM for multiple Link Layer usage. 0x82E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1048 Shared Packet RAM for multiple Link Layer usage. 0x830 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1049 Shared Packet RAM for multiple Link Layer usage. 0x832 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_105 Shared Packet RAM for multiple Link Layer usage. 0xD2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1050 Shared Packet RAM for multiple Link Layer usage. 0x834 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1051 Shared Packet RAM for multiple Link Layer usage. 0x836 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1052 Shared Packet RAM for multiple Link Layer usage. 0x838 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1053 Shared Packet RAM for multiple Link Layer usage. 0x83A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1054 Shared Packet RAM for multiple Link Layer usage. 0x83C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1055 Shared Packet RAM for multiple Link Layer usage. 0x83E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1056 Shared Packet RAM for multiple Link Layer usage. 0x840 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1057 Shared Packet RAM for multiple Link Layer usage. 0x842 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1058 Shared Packet RAM for multiple Link Layer usage. 0x844 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1059 Shared Packet RAM for multiple Link Layer usage. 0x846 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_106 Shared Packet RAM for multiple Link Layer usage. 0xD4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1060 Shared Packet RAM for multiple Link Layer usage. 0x848 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1061 Shared Packet RAM for multiple Link Layer usage. 0x84A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1062 Shared Packet RAM for multiple Link Layer usage. 0x84C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1063 Shared Packet RAM for multiple Link Layer usage. 0x84E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1064 Shared Packet RAM for multiple Link Layer usage. 0x850 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1065 Shared Packet RAM for multiple Link Layer usage. 0x852 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1066 Shared Packet RAM for multiple Link Layer usage. 0x854 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1067 Shared Packet RAM for multiple Link Layer usage. 0x856 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1068 Shared Packet RAM for multiple Link Layer usage. 0x858 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1069 Shared Packet RAM for multiple Link Layer usage. 0x85A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_107 Shared Packet RAM for multiple Link Layer usage. 0xD6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1070 Shared Packet RAM for multiple Link Layer usage. 0x85C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1071 Shared Packet RAM for multiple Link Layer usage. 0x85E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1072 Shared Packet RAM for multiple Link Layer usage. 0x860 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1073 Shared Packet RAM for multiple Link Layer usage. 0x862 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1074 Shared Packet RAM for multiple Link Layer usage. 0x864 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1075 Shared Packet RAM for multiple Link Layer usage. 0x866 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1076 Shared Packet RAM for multiple Link Layer usage. 0x868 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1077 Shared Packet RAM for multiple Link Layer usage. 0x86A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1078 Shared Packet RAM for multiple Link Layer usage. 0x86C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1079 Shared Packet RAM for multiple Link Layer usage. 0x86E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_108 Shared Packet RAM for multiple Link Layer usage. 0xD8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1080 Shared Packet RAM for multiple Link Layer usage. 0x870 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1081 Shared Packet RAM for multiple Link Layer usage. 0x872 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1082 Shared Packet RAM for multiple Link Layer usage. 0x874 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1083 Shared Packet RAM for multiple Link Layer usage. 0x876 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1084 Shared Packet RAM for multiple Link Layer usage. 0x878 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1085 Shared Packet RAM for multiple Link Layer usage. 0x87A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1086 Shared Packet RAM for multiple Link Layer usage. 0x87C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1087 Shared Packet RAM for multiple Link Layer usage. 0x87E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1088 Shared Packet RAM for multiple Link Layer usage. 0x880 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1089 Shared Packet RAM for multiple Link Layer usage. 0x882 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_109 Shared Packet RAM for multiple Link Layer usage. 0xDA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1090 Shared Packet RAM for multiple Link Layer usage. 0x884 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1091 Shared Packet RAM for multiple Link Layer usage. 0x886 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1092 Shared Packet RAM for multiple Link Layer usage. 0x888 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1093 Shared Packet RAM for multiple Link Layer usage. 0x88A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1094 Shared Packet RAM for multiple Link Layer usage. 0x88C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1095 Shared Packet RAM for multiple Link Layer usage. 0x88E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1096 Shared Packet RAM for multiple Link Layer usage. 0x890 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1097 Shared Packet RAM for multiple Link Layer usage. 0x892 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1098 Shared Packet RAM for multiple Link Layer usage. 0x894 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1099 Shared Packet RAM for multiple Link Layer usage. 0x896 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_11 Shared Packet RAM for multiple Link Layer usage. 0x16 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_110 Shared Packet RAM for multiple Link Layer usage. 0xDC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1100 Shared Packet RAM for multiple Link Layer usage. 0x898 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1101 Shared Packet RAM for multiple Link Layer usage. 0x89A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1102 Shared Packet RAM for multiple Link Layer usage. 0x89C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1103 Shared Packet RAM for multiple Link Layer usage. 0x89E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1104 Shared Packet RAM for multiple Link Layer usage. 0x8A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1105 Shared Packet RAM for multiple Link Layer usage. 0x8A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1106 Shared Packet RAM for multiple Link Layer usage. 0x8A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1107 Shared Packet RAM for multiple Link Layer usage. 0x8A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1108 Shared Packet RAM for multiple Link Layer usage. 0x8A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1109 Shared Packet RAM for multiple Link Layer usage. 0x8AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_111 Shared Packet RAM for multiple Link Layer usage. 0xDE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1110 Shared Packet RAM for multiple Link Layer usage. 0x8AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1111 Shared Packet RAM for multiple Link Layer usage. 0x8AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1112 Shared Packet RAM for multiple Link Layer usage. 0x8B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1113 Shared Packet RAM for multiple Link Layer usage. 0x8B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1114 Shared Packet RAM for multiple Link Layer usage. 0x8B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1115 Shared Packet RAM for multiple Link Layer usage. 0x8B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1116 Shared Packet RAM for multiple Link Layer usage. 0x8B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1117 Shared Packet RAM for multiple Link Layer usage. 0x8BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1118 Shared Packet RAM for multiple Link Layer usage. 0x8BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1119 Shared Packet RAM for multiple Link Layer usage. 0x8BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_112 Shared Packet RAM for multiple Link Layer usage. 0xE0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1120 Shared Packet RAM for multiple Link Layer usage. 0x8C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1121 Shared Packet RAM for multiple Link Layer usage. 0x8C2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1122 Shared Packet RAM for multiple Link Layer usage. 0x8C4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1123 Shared Packet RAM for multiple Link Layer usage. 0x8C6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1124 Shared Packet RAM for multiple Link Layer usage. 0x8C8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1125 Shared Packet RAM for multiple Link Layer usage. 0x8CA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1126 Shared Packet RAM for multiple Link Layer usage. 0x8CC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1127 Shared Packet RAM for multiple Link Layer usage. 0x8CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1128 Shared Packet RAM for multiple Link Layer usage. 0x8D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1129 Shared Packet RAM for multiple Link Layer usage. 0x8D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_113 Shared Packet RAM for multiple Link Layer usage. 0xE2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1130 Shared Packet RAM for multiple Link Layer usage. 0x8D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1131 Shared Packet RAM for multiple Link Layer usage. 0x8D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1132 Shared Packet RAM for multiple Link Layer usage. 0x8D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1133 Shared Packet RAM for multiple Link Layer usage. 0x8DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1134 Shared Packet RAM for multiple Link Layer usage. 0x8DC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1135 Shared Packet RAM for multiple Link Layer usage. 0x8DE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1136 Shared Packet RAM for multiple Link Layer usage. 0x8E0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1137 Shared Packet RAM for multiple Link Layer usage. 0x8E2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1138 Shared Packet RAM for multiple Link Layer usage. 0x8E4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1139 Shared Packet RAM for multiple Link Layer usage. 0x8E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_114 Shared Packet RAM for multiple Link Layer usage. 0xE4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1140 Shared Packet RAM for multiple Link Layer usage. 0x8E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1141 Shared Packet RAM for multiple Link Layer usage. 0x8EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1142 Shared Packet RAM for multiple Link Layer usage. 0x8EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1143 Shared Packet RAM for multiple Link Layer usage. 0x8EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1144 Shared Packet RAM for multiple Link Layer usage. 0x8F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1145 Shared Packet RAM for multiple Link Layer usage. 0x8F2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1146 Shared Packet RAM for multiple Link Layer usage. 0x8F4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1147 Shared Packet RAM for multiple Link Layer usage. 0x8F6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1148 Shared Packet RAM for multiple Link Layer usage. 0x8F8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1149 Shared Packet RAM for multiple Link Layer usage. 0x8FA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_115 Shared Packet RAM for multiple Link Layer usage. 0xE6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1150 Shared Packet RAM for multiple Link Layer usage. 0x8FC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_1151 Shared Packet RAM for multiple Link Layer usage. 0x8FE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_116 Shared Packet RAM for multiple Link Layer usage. 0xE8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_117 Shared Packet RAM for multiple Link Layer usage. 0xEA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_118 Shared Packet RAM for multiple Link Layer usage. 0xEC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_119 Shared Packet RAM for multiple Link Layer usage. 0xEE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_12 Shared Packet RAM for multiple Link Layer usage. 0x18 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_120 Shared Packet RAM for multiple Link Layer usage. 0xF0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_121 Shared Packet RAM for multiple Link Layer usage. 0xF2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_122 Shared Packet RAM for multiple Link Layer usage. 0xF4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_123 Shared Packet RAM for multiple Link Layer usage. 0xF6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_124 Shared Packet RAM for multiple Link Layer usage. 0xF8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_125 Shared Packet RAM for multiple Link Layer usage. 0xFA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_126 Shared Packet RAM for multiple Link Layer usage. 0xFC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_127 Shared Packet RAM for multiple Link Layer usage. 0xFE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_128 Shared Packet RAM for multiple Link Layer usage. 0x100 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_129 Shared Packet RAM for multiple Link Layer usage. 0x102 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_13 Shared Packet RAM for multiple Link Layer usage. 0x1A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_130 Shared Packet RAM for multiple Link Layer usage. 0x104 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_131 Shared Packet RAM for multiple Link Layer usage. 0x106 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_132 Shared Packet RAM for multiple Link Layer usage. 0x108 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_133 Shared Packet RAM for multiple Link Layer usage. 0x10A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_134 Shared Packet RAM for multiple Link Layer usage. 0x10C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_135 Shared Packet RAM for multiple Link Layer usage. 0x10E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_136 Shared Packet RAM for multiple Link Layer usage. 0x110 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_137 Shared Packet RAM for multiple Link Layer usage. 0x112 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_138 Shared Packet RAM for multiple Link Layer usage. 0x114 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_139 Shared Packet RAM for multiple Link Layer usage. 0x116 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_14 Shared Packet RAM for multiple Link Layer usage. 0x1C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_140 Shared Packet RAM for multiple Link Layer usage. 0x118 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_141 Shared Packet RAM for multiple Link Layer usage. 0x11A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_142 Shared Packet RAM for multiple Link Layer usage. 0x11C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_143 Shared Packet RAM for multiple Link Layer usage. 0x11E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_144 Shared Packet RAM for multiple Link Layer usage. 0x120 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_145 Shared Packet RAM for multiple Link Layer usage. 0x122 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_146 Shared Packet RAM for multiple Link Layer usage. 0x124 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_147 Shared Packet RAM for multiple Link Layer usage. 0x126 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_148 Shared Packet RAM for multiple Link Layer usage. 0x128 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_149 Shared Packet RAM for multiple Link Layer usage. 0x12A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_15 Shared Packet RAM for multiple Link Layer usage. 0x1E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_150 Shared Packet RAM for multiple Link Layer usage. 0x12C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_151 Shared Packet RAM for multiple Link Layer usage. 0x12E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_152 Shared Packet RAM for multiple Link Layer usage. 0x130 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_153 Shared Packet RAM for multiple Link Layer usage. 0x132 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_154 Shared Packet RAM for multiple Link Layer usage. 0x134 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_155 Shared Packet RAM for multiple Link Layer usage. 0x136 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_156 Shared Packet RAM for multiple Link Layer usage. 0x138 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_157 Shared Packet RAM for multiple Link Layer usage. 0x13A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_158 Shared Packet RAM for multiple Link Layer usage. 0x13C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_159 Shared Packet RAM for multiple Link Layer usage. 0x13E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_16 Shared Packet RAM for multiple Link Layer usage. 0x20 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_160 Shared Packet RAM for multiple Link Layer usage. 0x140 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_161 Shared Packet RAM for multiple Link Layer usage. 0x142 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_162 Shared Packet RAM for multiple Link Layer usage. 0x144 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_163 Shared Packet RAM for multiple Link Layer usage. 0x146 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_164 Shared Packet RAM for multiple Link Layer usage. 0x148 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_165 Shared Packet RAM for multiple Link Layer usage. 0x14A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_166 Shared Packet RAM for multiple Link Layer usage. 0x14C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_167 Shared Packet RAM for multiple Link Layer usage. 0x14E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_168 Shared Packet RAM for multiple Link Layer usage. 0x150 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_169 Shared Packet RAM for multiple Link Layer usage. 0x152 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_17 Shared Packet RAM for multiple Link Layer usage. 0x22 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_170 Shared Packet RAM for multiple Link Layer usage. 0x154 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_171 Shared Packet RAM for multiple Link Layer usage. 0x156 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_172 Shared Packet RAM for multiple Link Layer usage. 0x158 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_173 Shared Packet RAM for multiple Link Layer usage. 0x15A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_174 Shared Packet RAM for multiple Link Layer usage. 0x15C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_175 Shared Packet RAM for multiple Link Layer usage. 0x15E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_176 Shared Packet RAM for multiple Link Layer usage. 0x160 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_177 Shared Packet RAM for multiple Link Layer usage. 0x162 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_178 Shared Packet RAM for multiple Link Layer usage. 0x164 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_179 Shared Packet RAM for multiple Link Layer usage. 0x166 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_18 Shared Packet RAM for multiple Link Layer usage. 0x24 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_180 Shared Packet RAM for multiple Link Layer usage. 0x168 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_181 Shared Packet RAM for multiple Link Layer usage. 0x16A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_182 Shared Packet RAM for multiple Link Layer usage. 0x16C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_183 Shared Packet RAM for multiple Link Layer usage. 0x16E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_184 Shared Packet RAM for multiple Link Layer usage. 0x170 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_185 Shared Packet RAM for multiple Link Layer usage. 0x172 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_186 Shared Packet RAM for multiple Link Layer usage. 0x174 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_187 Shared Packet RAM for multiple Link Layer usage. 0x176 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_188 Shared Packet RAM for multiple Link Layer usage. 0x178 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_189 Shared Packet RAM for multiple Link Layer usage. 0x17A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_19 Shared Packet RAM for multiple Link Layer usage. 0x26 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_190 Shared Packet RAM for multiple Link Layer usage. 0x17C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_191 Shared Packet RAM for multiple Link Layer usage. 0x17E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_192 Shared Packet RAM for multiple Link Layer usage. 0x180 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_193 Shared Packet RAM for multiple Link Layer usage. 0x182 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_194 Shared Packet RAM for multiple Link Layer usage. 0x184 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_195 Shared Packet RAM for multiple Link Layer usage. 0x186 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_196 Shared Packet RAM for multiple Link Layer usage. 0x188 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_197 Shared Packet RAM for multiple Link Layer usage. 0x18A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_198 Shared Packet RAM for multiple Link Layer usage. 0x18C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_199 Shared Packet RAM for multiple Link Layer usage. 0x18E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_2 Shared Packet RAM for multiple Link Layer usage. 0x4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_20 Shared Packet RAM for multiple Link Layer usage. 0x28 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_200 Shared Packet RAM for multiple Link Layer usage. 0x190 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_201 Shared Packet RAM for multiple Link Layer usage. 0x192 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_202 Shared Packet RAM for multiple Link Layer usage. 0x194 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_203 Shared Packet RAM for multiple Link Layer usage. 0x196 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_204 Shared Packet RAM for multiple Link Layer usage. 0x198 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_205 Shared Packet RAM for multiple Link Layer usage. 0x19A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_206 Shared Packet RAM for multiple Link Layer usage. 0x19C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_207 Shared Packet RAM for multiple Link Layer usage. 0x19E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_208 Shared Packet RAM for multiple Link Layer usage. 0x1A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_209 Shared Packet RAM for multiple Link Layer usage. 0x1A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_21 Shared Packet RAM for multiple Link Layer usage. 0x2A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_210 Shared Packet RAM for multiple Link Layer usage. 0x1A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_211 Shared Packet RAM for multiple Link Layer usage. 0x1A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_212 Shared Packet RAM for multiple Link Layer usage. 0x1A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_213 Shared Packet RAM for multiple Link Layer usage. 0x1AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_214 Shared Packet RAM for multiple Link Layer usage. 0x1AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_215 Shared Packet RAM for multiple Link Layer usage. 0x1AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_216 Shared Packet RAM for multiple Link Layer usage. 0x1B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_217 Shared Packet RAM for multiple Link Layer usage. 0x1B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_218 Shared Packet RAM for multiple Link Layer usage. 0x1B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_219 Shared Packet RAM for multiple Link Layer usage. 0x1B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_22 Shared Packet RAM for multiple Link Layer usage. 0x2C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_220 Shared Packet RAM for multiple Link Layer usage. 0x1B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_221 Shared Packet RAM for multiple Link Layer usage. 0x1BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_222 Shared Packet RAM for multiple Link Layer usage. 0x1BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_223 Shared Packet RAM for multiple Link Layer usage. 0x1BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_224 Shared Packet RAM for multiple Link Layer usage. 0x1C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_225 Shared Packet RAM for multiple Link Layer usage. 0x1C2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_226 Shared Packet RAM for multiple Link Layer usage. 0x1C4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_227 Shared Packet RAM for multiple Link Layer usage. 0x1C6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_228 Shared Packet RAM for multiple Link Layer usage. 0x1C8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_229 Shared Packet RAM for multiple Link Layer usage. 0x1CA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_23 Shared Packet RAM for multiple Link Layer usage. 0x2E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_230 Shared Packet RAM for multiple Link Layer usage. 0x1CC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_231 Shared Packet RAM for multiple Link Layer usage. 0x1CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_232 Shared Packet RAM for multiple Link Layer usage. 0x1D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_233 Shared Packet RAM for multiple Link Layer usage. 0x1D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_234 Shared Packet RAM for multiple Link Layer usage. 0x1D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_235 Shared Packet RAM for multiple Link Layer usage. 0x1D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_236 Shared Packet RAM for multiple Link Layer usage. 0x1D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_237 Shared Packet RAM for multiple Link Layer usage. 0x1DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_238 Shared Packet RAM for multiple Link Layer usage. 0x1DC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_239 Shared Packet RAM for multiple Link Layer usage. 0x1DE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_24 Shared Packet RAM for multiple Link Layer usage. 0x30 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_240 Shared Packet RAM for multiple Link Layer usage. 0x1E0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_241 Shared Packet RAM for multiple Link Layer usage. 0x1E2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_242 Shared Packet RAM for multiple Link Layer usage. 0x1E4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_243 Shared Packet RAM for multiple Link Layer usage. 0x1E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_244 Shared Packet RAM for multiple Link Layer usage. 0x1E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_245 Shared Packet RAM for multiple Link Layer usage. 0x1EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_246 Shared Packet RAM for multiple Link Layer usage. 0x1EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_247 Shared Packet RAM for multiple Link Layer usage. 0x1EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_248 Shared Packet RAM for multiple Link Layer usage. 0x1F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_249 Shared Packet RAM for multiple Link Layer usage. 0x1F2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_25 Shared Packet RAM for multiple Link Layer usage. 0x32 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_250 Shared Packet RAM for multiple Link Layer usage. 0x1F4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_251 Shared Packet RAM for multiple Link Layer usage. 0x1F6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_252 Shared Packet RAM for multiple Link Layer usage. 0x1F8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_253 Shared Packet RAM for multiple Link Layer usage. 0x1FA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_254 Shared Packet RAM for multiple Link Layer usage. 0x1FC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_255 Shared Packet RAM for multiple Link Layer usage. 0x1FE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_256 Shared Packet RAM for multiple Link Layer usage. 0x200 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_257 Shared Packet RAM for multiple Link Layer usage. 0x202 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_258 Shared Packet RAM for multiple Link Layer usage. 0x204 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_259 Shared Packet RAM for multiple Link Layer usage. 0x206 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_26 Shared Packet RAM for multiple Link Layer usage. 0x34 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_260 Shared Packet RAM for multiple Link Layer usage. 0x208 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_261 Shared Packet RAM for multiple Link Layer usage. 0x20A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_262 Shared Packet RAM for multiple Link Layer usage. 0x20C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_263 Shared Packet RAM for multiple Link Layer usage. 0x20E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_264 Shared Packet RAM for multiple Link Layer usage. 0x210 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_265 Shared Packet RAM for multiple Link Layer usage. 0x212 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_266 Shared Packet RAM for multiple Link Layer usage. 0x214 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_267 Shared Packet RAM for multiple Link Layer usage. 0x216 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_268 Shared Packet RAM for multiple Link Layer usage. 0x218 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_269 Shared Packet RAM for multiple Link Layer usage. 0x21A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_27 Shared Packet RAM for multiple Link Layer usage. 0x36 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_270 Shared Packet RAM for multiple Link Layer usage. 0x21C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_271 Shared Packet RAM for multiple Link Layer usage. 0x21E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_272 Shared Packet RAM for multiple Link Layer usage. 0x220 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_273 Shared Packet RAM for multiple Link Layer usage. 0x222 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_274 Shared Packet RAM for multiple Link Layer usage. 0x224 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_275 Shared Packet RAM for multiple Link Layer usage. 0x226 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_276 Shared Packet RAM for multiple Link Layer usage. 0x228 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_277 Shared Packet RAM for multiple Link Layer usage. 0x22A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_278 Shared Packet RAM for multiple Link Layer usage. 0x22C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_279 Shared Packet RAM for multiple Link Layer usage. 0x22E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_28 Shared Packet RAM for multiple Link Layer usage. 0x38 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_280 Shared Packet RAM for multiple Link Layer usage. 0x230 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_281 Shared Packet RAM for multiple Link Layer usage. 0x232 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_282 Shared Packet RAM for multiple Link Layer usage. 0x234 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_283 Shared Packet RAM for multiple Link Layer usage. 0x236 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_284 Shared Packet RAM for multiple Link Layer usage. 0x238 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_285 Shared Packet RAM for multiple Link Layer usage. 0x23A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_286 Shared Packet RAM for multiple Link Layer usage. 0x23C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_287 Shared Packet RAM for multiple Link Layer usage. 0x23E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_288 Shared Packet RAM for multiple Link Layer usage. 0x240 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_289 Shared Packet RAM for multiple Link Layer usage. 0x242 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_29 Shared Packet RAM for multiple Link Layer usage. 0x3A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_290 Shared Packet RAM for multiple Link Layer usage. 0x244 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_291 Shared Packet RAM for multiple Link Layer usage. 0x246 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_292 Shared Packet RAM for multiple Link Layer usage. 0x248 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_293 Shared Packet RAM for multiple Link Layer usage. 0x24A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_294 Shared Packet RAM for multiple Link Layer usage. 0x24C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_295 Shared Packet RAM for multiple Link Layer usage. 0x24E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_296 Shared Packet RAM for multiple Link Layer usage. 0x250 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_297 Shared Packet RAM for multiple Link Layer usage. 0x252 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_298 Shared Packet RAM for multiple Link Layer usage. 0x254 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_299 Shared Packet RAM for multiple Link Layer usage. 0x256 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_3 Shared Packet RAM for multiple Link Layer usage. 0x6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_30 Shared Packet RAM for multiple Link Layer usage. 0x3C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_300 Shared Packet RAM for multiple Link Layer usage. 0x258 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_301 Shared Packet RAM for multiple Link Layer usage. 0x25A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_302 Shared Packet RAM for multiple Link Layer usage. 0x25C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_303 Shared Packet RAM for multiple Link Layer usage. 0x25E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_304 Shared Packet RAM for multiple Link Layer usage. 0x260 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_305 Shared Packet RAM for multiple Link Layer usage. 0x262 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_306 Shared Packet RAM for multiple Link Layer usage. 0x264 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_307 Shared Packet RAM for multiple Link Layer usage. 0x266 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_308 Shared Packet RAM for multiple Link Layer usage. 0x268 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_309 Shared Packet RAM for multiple Link Layer usage. 0x26A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_31 Shared Packet RAM for multiple Link Layer usage. 0x3E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_310 Shared Packet RAM for multiple Link Layer usage. 0x26C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_311 Shared Packet RAM for multiple Link Layer usage. 0x26E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_312 Shared Packet RAM for multiple Link Layer usage. 0x270 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_313 Shared Packet RAM for multiple Link Layer usage. 0x272 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_314 Shared Packet RAM for multiple Link Layer usage. 0x274 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_315 Shared Packet RAM for multiple Link Layer usage. 0x276 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_316 Shared Packet RAM for multiple Link Layer usage. 0x278 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_317 Shared Packet RAM for multiple Link Layer usage. 0x27A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_318 Shared Packet RAM for multiple Link Layer usage. 0x27C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_319 Shared Packet RAM for multiple Link Layer usage. 0x27E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_32 Shared Packet RAM for multiple Link Layer usage. 0x40 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_320 Shared Packet RAM for multiple Link Layer usage. 0x280 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_321 Shared Packet RAM for multiple Link Layer usage. 0x282 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_322 Shared Packet RAM for multiple Link Layer usage. 0x284 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_323 Shared Packet RAM for multiple Link Layer usage. 0x286 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_324 Shared Packet RAM for multiple Link Layer usage. 0x288 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_325 Shared Packet RAM for multiple Link Layer usage. 0x28A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_326 Shared Packet RAM for multiple Link Layer usage. 0x28C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_327 Shared Packet RAM for multiple Link Layer usage. 0x28E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_328 Shared Packet RAM for multiple Link Layer usage. 0x290 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_329 Shared Packet RAM for multiple Link Layer usage. 0x292 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_33 Shared Packet RAM for multiple Link Layer usage. 0x42 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_330 Shared Packet RAM for multiple Link Layer usage. 0x294 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_331 Shared Packet RAM for multiple Link Layer usage. 0x296 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_332 Shared Packet RAM for multiple Link Layer usage. 0x298 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_333 Shared Packet RAM for multiple Link Layer usage. 0x29A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_334 Shared Packet RAM for multiple Link Layer usage. 0x29C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_335 Shared Packet RAM for multiple Link Layer usage. 0x29E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_336 Shared Packet RAM for multiple Link Layer usage. 0x2A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_337 Shared Packet RAM for multiple Link Layer usage. 0x2A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_338 Shared Packet RAM for multiple Link Layer usage. 0x2A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_339 Shared Packet RAM for multiple Link Layer usage. 0x2A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_34 Shared Packet RAM for multiple Link Layer usage. 0x44 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_340 Shared Packet RAM for multiple Link Layer usage. 0x2A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_341 Shared Packet RAM for multiple Link Layer usage. 0x2AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_342 Shared Packet RAM for multiple Link Layer usage. 0x2AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_343 Shared Packet RAM for multiple Link Layer usage. 0x2AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_344 Shared Packet RAM for multiple Link Layer usage. 0x2B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_345 Shared Packet RAM for multiple Link Layer usage. 0x2B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_346 Shared Packet RAM for multiple Link Layer usage. 0x2B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_347 Shared Packet RAM for multiple Link Layer usage. 0x2B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_348 Shared Packet RAM for multiple Link Layer usage. 0x2B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_349 Shared Packet RAM for multiple Link Layer usage. 0x2BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_35 Shared Packet RAM for multiple Link Layer usage. 0x46 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_350 Shared Packet RAM for multiple Link Layer usage. 0x2BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_351 Shared Packet RAM for multiple Link Layer usage. 0x2BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_352 Shared Packet RAM for multiple Link Layer usage. 0x2C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_353 Shared Packet RAM for multiple Link Layer usage. 0x2C2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_354 Shared Packet RAM for multiple Link Layer usage. 0x2C4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_355 Shared Packet RAM for multiple Link Layer usage. 0x2C6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_356 Shared Packet RAM for multiple Link Layer usage. 0x2C8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_357 Shared Packet RAM for multiple Link Layer usage. 0x2CA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_358 Shared Packet RAM for multiple Link Layer usage. 0x2CC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_359 Shared Packet RAM for multiple Link Layer usage. 0x2CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_36 Shared Packet RAM for multiple Link Layer usage. 0x48 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_360 Shared Packet RAM for multiple Link Layer usage. 0x2D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_361 Shared Packet RAM for multiple Link Layer usage. 0x2D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_362 Shared Packet RAM for multiple Link Layer usage. 0x2D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_363 Shared Packet RAM for multiple Link Layer usage. 0x2D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_364 Shared Packet RAM for multiple Link Layer usage. 0x2D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_365 Shared Packet RAM for multiple Link Layer usage. 0x2DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_366 Shared Packet RAM for multiple Link Layer usage. 0x2DC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_367 Shared Packet RAM for multiple Link Layer usage. 0x2DE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_368 Shared Packet RAM for multiple Link Layer usage. 0x2E0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_369 Shared Packet RAM for multiple Link Layer usage. 0x2E2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_37 Shared Packet RAM for multiple Link Layer usage. 0x4A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_370 Shared Packet RAM for multiple Link Layer usage. 0x2E4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_371 Shared Packet RAM for multiple Link Layer usage. 0x2E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_372 Shared Packet RAM for multiple Link Layer usage. 0x2E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_373 Shared Packet RAM for multiple Link Layer usage. 0x2EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_374 Shared Packet RAM for multiple Link Layer usage. 0x2EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_375 Shared Packet RAM for multiple Link Layer usage. 0x2EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_376 Shared Packet RAM for multiple Link Layer usage. 0x2F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_377 Shared Packet RAM for multiple Link Layer usage. 0x2F2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_378 Shared Packet RAM for multiple Link Layer usage. 0x2F4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_379 Shared Packet RAM for multiple Link Layer usage. 0x2F6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_38 Shared Packet RAM for multiple Link Layer usage. 0x4C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_380 Shared Packet RAM for multiple Link Layer usage. 0x2F8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_381 Shared Packet RAM for multiple Link Layer usage. 0x2FA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_382 Shared Packet RAM for multiple Link Layer usage. 0x2FC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_383 Shared Packet RAM for multiple Link Layer usage. 0x2FE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_384 Shared Packet RAM for multiple Link Layer usage. 0x300 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_385 Shared Packet RAM for multiple Link Layer usage. 0x302 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_386 Shared Packet RAM for multiple Link Layer usage. 0x304 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_387 Shared Packet RAM for multiple Link Layer usage. 0x306 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_388 Shared Packet RAM for multiple Link Layer usage. 0x308 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_389 Shared Packet RAM for multiple Link Layer usage. 0x30A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_39 Shared Packet RAM for multiple Link Layer usage. 0x4E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_390 Shared Packet RAM for multiple Link Layer usage. 0x30C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_391 Shared Packet RAM for multiple Link Layer usage. 0x30E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_392 Shared Packet RAM for multiple Link Layer usage. 0x310 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_393 Shared Packet RAM for multiple Link Layer usage. 0x312 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_394 Shared Packet RAM for multiple Link Layer usage. 0x314 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_395 Shared Packet RAM for multiple Link Layer usage. 0x316 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_396 Shared Packet RAM for multiple Link Layer usage. 0x318 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_397 Shared Packet RAM for multiple Link Layer usage. 0x31A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_398 Shared Packet RAM for multiple Link Layer usage. 0x31C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_399 Shared Packet RAM for multiple Link Layer usage. 0x31E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_4 Shared Packet RAM for multiple Link Layer usage. 0x8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_40 Shared Packet RAM for multiple Link Layer usage. 0x50 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_400 Shared Packet RAM for multiple Link Layer usage. 0x320 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_401 Shared Packet RAM for multiple Link Layer usage. 0x322 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_402 Shared Packet RAM for multiple Link Layer usage. 0x324 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_403 Shared Packet RAM for multiple Link Layer usage. 0x326 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_404 Shared Packet RAM for multiple Link Layer usage. 0x328 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_405 Shared Packet RAM for multiple Link Layer usage. 0x32A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_406 Shared Packet RAM for multiple Link Layer usage. 0x32C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_407 Shared Packet RAM for multiple Link Layer usage. 0x32E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_408 Shared Packet RAM for multiple Link Layer usage. 0x330 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_409 Shared Packet RAM for multiple Link Layer usage. 0x332 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_41 Shared Packet RAM for multiple Link Layer usage. 0x52 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_410 Shared Packet RAM for multiple Link Layer usage. 0x334 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_411 Shared Packet RAM for multiple Link Layer usage. 0x336 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_412 Shared Packet RAM for multiple Link Layer usage. 0x338 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_413 Shared Packet RAM for multiple Link Layer usage. 0x33A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_414 Shared Packet RAM for multiple Link Layer usage. 0x33C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_415 Shared Packet RAM for multiple Link Layer usage. 0x33E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_416 Shared Packet RAM for multiple Link Layer usage. 0x340 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_417 Shared Packet RAM for multiple Link Layer usage. 0x342 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_418 Shared Packet RAM for multiple Link Layer usage. 0x344 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_419 Shared Packet RAM for multiple Link Layer usage. 0x346 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_42 Shared Packet RAM for multiple Link Layer usage. 0x54 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_420 Shared Packet RAM for multiple Link Layer usage. 0x348 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_421 Shared Packet RAM for multiple Link Layer usage. 0x34A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_422 Shared Packet RAM for multiple Link Layer usage. 0x34C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_423 Shared Packet RAM for multiple Link Layer usage. 0x34E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_424 Shared Packet RAM for multiple Link Layer usage. 0x350 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_425 Shared Packet RAM for multiple Link Layer usage. 0x352 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_426 Shared Packet RAM for multiple Link Layer usage. 0x354 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_427 Shared Packet RAM for multiple Link Layer usage. 0x356 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_428 Shared Packet RAM for multiple Link Layer usage. 0x358 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_429 Shared Packet RAM for multiple Link Layer usage. 0x35A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_43 Shared Packet RAM for multiple Link Layer usage. 0x56 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_430 Shared Packet RAM for multiple Link Layer usage. 0x35C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_431 Shared Packet RAM for multiple Link Layer usage. 0x35E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_432 Shared Packet RAM for multiple Link Layer usage. 0x360 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_433 Shared Packet RAM for multiple Link Layer usage. 0x362 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_434 Shared Packet RAM for multiple Link Layer usage. 0x364 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_435 Shared Packet RAM for multiple Link Layer usage. 0x366 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_436 Shared Packet RAM for multiple Link Layer usage. 0x368 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_437 Shared Packet RAM for multiple Link Layer usage. 0x36A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_438 Shared Packet RAM for multiple Link Layer usage. 0x36C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_439 Shared Packet RAM for multiple Link Layer usage. 0x36E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_44 Shared Packet RAM for multiple Link Layer usage. 0x58 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_440 Shared Packet RAM for multiple Link Layer usage. 0x370 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_441 Shared Packet RAM for multiple Link Layer usage. 0x372 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_442 Shared Packet RAM for multiple Link Layer usage. 0x374 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_443 Shared Packet RAM for multiple Link Layer usage. 0x376 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_444 Shared Packet RAM for multiple Link Layer usage. 0x378 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_445 Shared Packet RAM for multiple Link Layer usage. 0x37A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_446 Shared Packet RAM for multiple Link Layer usage. 0x37C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_447 Shared Packet RAM for multiple Link Layer usage. 0x37E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_448 Shared Packet RAM for multiple Link Layer usage. 0x380 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_449 Shared Packet RAM for multiple Link Layer usage. 0x382 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_45 Shared Packet RAM for multiple Link Layer usage. 0x5A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_450 Shared Packet RAM for multiple Link Layer usage. 0x384 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_451 Shared Packet RAM for multiple Link Layer usage. 0x386 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_452 Shared Packet RAM for multiple Link Layer usage. 0x388 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_453 Shared Packet RAM for multiple Link Layer usage. 0x38A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_454 Shared Packet RAM for multiple Link Layer usage. 0x38C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_455 Shared Packet RAM for multiple Link Layer usage. 0x38E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_456 Shared Packet RAM for multiple Link Layer usage. 0x390 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_457 Shared Packet RAM for multiple Link Layer usage. 0x392 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_458 Shared Packet RAM for multiple Link Layer usage. 0x394 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_459 Shared Packet RAM for multiple Link Layer usage. 0x396 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_46 Shared Packet RAM for multiple Link Layer usage. 0x5C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_460 Shared Packet RAM for multiple Link Layer usage. 0x398 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_461 Shared Packet RAM for multiple Link Layer usage. 0x39A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_462 Shared Packet RAM for multiple Link Layer usage. 0x39C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_463 Shared Packet RAM for multiple Link Layer usage. 0x39E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_464 Shared Packet RAM for multiple Link Layer usage. 0x3A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_465 Shared Packet RAM for multiple Link Layer usage. 0x3A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_466 Shared Packet RAM for multiple Link Layer usage. 0x3A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_467 Shared Packet RAM for multiple Link Layer usage. 0x3A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_468 Shared Packet RAM for multiple Link Layer usage. 0x3A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_469 Shared Packet RAM for multiple Link Layer usage. 0x3AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_47 Shared Packet RAM for multiple Link Layer usage. 0x5E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_470 Shared Packet RAM for multiple Link Layer usage. 0x3AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_471 Shared Packet RAM for multiple Link Layer usage. 0x3AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_472 Shared Packet RAM for multiple Link Layer usage. 0x3B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_473 Shared Packet RAM for multiple Link Layer usage. 0x3B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_474 Shared Packet RAM for multiple Link Layer usage. 0x3B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_475 Shared Packet RAM for multiple Link Layer usage. 0x3B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_476 Shared Packet RAM for multiple Link Layer usage. 0x3B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_477 Shared Packet RAM for multiple Link Layer usage. 0x3BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_478 Shared Packet RAM for multiple Link Layer usage. 0x3BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_479 Shared Packet RAM for multiple Link Layer usage. 0x3BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_48 Shared Packet RAM for multiple Link Layer usage. 0x60 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_480 Shared Packet RAM for multiple Link Layer usage. 0x3C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_481 Shared Packet RAM for multiple Link Layer usage. 0x3C2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_482 Shared Packet RAM for multiple Link Layer usage. 0x3C4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_483 Shared Packet RAM for multiple Link Layer usage. 0x3C6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_484 Shared Packet RAM for multiple Link Layer usage. 0x3C8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_485 Shared Packet RAM for multiple Link Layer usage. 0x3CA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_486 Shared Packet RAM for multiple Link Layer usage. 0x3CC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_487 Shared Packet RAM for multiple Link Layer usage. 0x3CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_488 Shared Packet RAM for multiple Link Layer usage. 0x3D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_489 Shared Packet RAM for multiple Link Layer usage. 0x3D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_49 Shared Packet RAM for multiple Link Layer usage. 0x62 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_490 Shared Packet RAM for multiple Link Layer usage. 0x3D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_491 Shared Packet RAM for multiple Link Layer usage. 0x3D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_492 Shared Packet RAM for multiple Link Layer usage. 0x3D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_493 Shared Packet RAM for multiple Link Layer usage. 0x3DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_494 Shared Packet RAM for multiple Link Layer usage. 0x3DC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_495 Shared Packet RAM for multiple Link Layer usage. 0x3DE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_496 Shared Packet RAM for multiple Link Layer usage. 0x3E0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_497 Shared Packet RAM for multiple Link Layer usage. 0x3E2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_498 Shared Packet RAM for multiple Link Layer usage. 0x3E4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_499 Shared Packet RAM for multiple Link Layer usage. 0x3E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_5 Shared Packet RAM for multiple Link Layer usage. 0xA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_50 Shared Packet RAM for multiple Link Layer usage. 0x64 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_500 Shared Packet RAM for multiple Link Layer usage. 0x3E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_501 Shared Packet RAM for multiple Link Layer usage. 0x3EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_502 Shared Packet RAM for multiple Link Layer usage. 0x3EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_503 Shared Packet RAM for multiple Link Layer usage. 0x3EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_504 Shared Packet RAM for multiple Link Layer usage. 0x3F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_505 Shared Packet RAM for multiple Link Layer usage. 0x3F2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_506 Shared Packet RAM for multiple Link Layer usage. 0x3F4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_507 Shared Packet RAM for multiple Link Layer usage. 0x3F6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_508 Shared Packet RAM for multiple Link Layer usage. 0x3F8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_509 Shared Packet RAM for multiple Link Layer usage. 0x3FA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_51 Shared Packet RAM for multiple Link Layer usage. 0x66 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_510 Shared Packet RAM for multiple Link Layer usage. 0x3FC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_511 Shared Packet RAM for multiple Link Layer usage. 0x3FE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_512 Shared Packet RAM for multiple Link Layer usage. 0x400 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_513 Shared Packet RAM for multiple Link Layer usage. 0x402 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_514 Shared Packet RAM for multiple Link Layer usage. 0x404 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_515 Shared Packet RAM for multiple Link Layer usage. 0x406 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_516 Shared Packet RAM for multiple Link Layer usage. 0x408 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_517 Shared Packet RAM for multiple Link Layer usage. 0x40A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_518 Shared Packet RAM for multiple Link Layer usage. 0x40C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_519 Shared Packet RAM for multiple Link Layer usage. 0x40E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_52 Shared Packet RAM for multiple Link Layer usage. 0x68 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_520 Shared Packet RAM for multiple Link Layer usage. 0x410 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_521 Shared Packet RAM for multiple Link Layer usage. 0x412 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_522 Shared Packet RAM for multiple Link Layer usage. 0x414 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_523 Shared Packet RAM for multiple Link Layer usage. 0x416 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_524 Shared Packet RAM for multiple Link Layer usage. 0x418 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_525 Shared Packet RAM for multiple Link Layer usage. 0x41A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_526 Shared Packet RAM for multiple Link Layer usage. 0x41C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_527 Shared Packet RAM for multiple Link Layer usage. 0x41E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_528 Shared Packet RAM for multiple Link Layer usage. 0x420 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_529 Shared Packet RAM for multiple Link Layer usage. 0x422 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_53 Shared Packet RAM for multiple Link Layer usage. 0x6A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_530 Shared Packet RAM for multiple Link Layer usage. 0x424 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_531 Shared Packet RAM for multiple Link Layer usage. 0x426 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_532 Shared Packet RAM for multiple Link Layer usage. 0x428 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_533 Shared Packet RAM for multiple Link Layer usage. 0x42A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_534 Shared Packet RAM for multiple Link Layer usage. 0x42C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_535 Shared Packet RAM for multiple Link Layer usage. 0x42E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_536 Shared Packet RAM for multiple Link Layer usage. 0x430 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_537 Shared Packet RAM for multiple Link Layer usage. 0x432 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_538 Shared Packet RAM for multiple Link Layer usage. 0x434 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_539 Shared Packet RAM for multiple Link Layer usage. 0x436 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_54 Shared Packet RAM for multiple Link Layer usage. 0x6C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_540 Shared Packet RAM for multiple Link Layer usage. 0x438 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_541 Shared Packet RAM for multiple Link Layer usage. 0x43A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_542 Shared Packet RAM for multiple Link Layer usage. 0x43C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_543 Shared Packet RAM for multiple Link Layer usage. 0x43E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_544 Shared Packet RAM for multiple Link Layer usage. 0x440 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_545 Shared Packet RAM for multiple Link Layer usage. 0x442 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_546 Shared Packet RAM for multiple Link Layer usage. 0x444 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_547 Shared Packet RAM for multiple Link Layer usage. 0x446 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_548 Shared Packet RAM for multiple Link Layer usage. 0x448 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_549 Shared Packet RAM for multiple Link Layer usage. 0x44A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_55 Shared Packet RAM for multiple Link Layer usage. 0x6E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_550 Shared Packet RAM for multiple Link Layer usage. 0x44C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_551 Shared Packet RAM for multiple Link Layer usage. 0x44E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_552 Shared Packet RAM for multiple Link Layer usage. 0x450 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_553 Shared Packet RAM for multiple Link Layer usage. 0x452 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_554 Shared Packet RAM for multiple Link Layer usage. 0x454 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_555 Shared Packet RAM for multiple Link Layer usage. 0x456 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_556 Shared Packet RAM for multiple Link Layer usage. 0x458 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_557 Shared Packet RAM for multiple Link Layer usage. 0x45A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_558 Shared Packet RAM for multiple Link Layer usage. 0x45C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_559 Shared Packet RAM for multiple Link Layer usage. 0x45E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_56 Shared Packet RAM for multiple Link Layer usage. 0x70 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_560 Shared Packet RAM for multiple Link Layer usage. 0x460 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_561 Shared Packet RAM for multiple Link Layer usage. 0x462 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_562 Shared Packet RAM for multiple Link Layer usage. 0x464 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_563 Shared Packet RAM for multiple Link Layer usage. 0x466 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_564 Shared Packet RAM for multiple Link Layer usage. 0x468 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_565 Shared Packet RAM for multiple Link Layer usage. 0x46A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_566 Shared Packet RAM for multiple Link Layer usage. 0x46C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_567 Shared Packet RAM for multiple Link Layer usage. 0x46E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_568 Shared Packet RAM for multiple Link Layer usage. 0x470 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_569 Shared Packet RAM for multiple Link Layer usage. 0x472 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_57 Shared Packet RAM for multiple Link Layer usage. 0x72 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_570 Shared Packet RAM for multiple Link Layer usage. 0x474 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_571 Shared Packet RAM for multiple Link Layer usage. 0x476 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_572 Shared Packet RAM for multiple Link Layer usage. 0x478 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_573 Shared Packet RAM for multiple Link Layer usage. 0x47A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_574 Shared Packet RAM for multiple Link Layer usage. 0x47C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_575 Shared Packet RAM for multiple Link Layer usage. 0x47E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_576 Shared Packet RAM for multiple Link Layer usage. 0x480 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_577 Shared Packet RAM for multiple Link Layer usage. 0x482 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_578 Shared Packet RAM for multiple Link Layer usage. 0x484 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_579 Shared Packet RAM for multiple Link Layer usage. 0x486 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_58 Shared Packet RAM for multiple Link Layer usage. 0x74 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_580 Shared Packet RAM for multiple Link Layer usage. 0x488 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_581 Shared Packet RAM for multiple Link Layer usage. 0x48A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_582 Shared Packet RAM for multiple Link Layer usage. 0x48C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_583 Shared Packet RAM for multiple Link Layer usage. 0x48E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_584 Shared Packet RAM for multiple Link Layer usage. 0x490 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_585 Shared Packet RAM for multiple Link Layer usage. 0x492 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_586 Shared Packet RAM for multiple Link Layer usage. 0x494 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_587 Shared Packet RAM for multiple Link Layer usage. 0x496 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_588 Shared Packet RAM for multiple Link Layer usage. 0x498 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_589 Shared Packet RAM for multiple Link Layer usage. 0x49A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_59 Shared Packet RAM for multiple Link Layer usage. 0x76 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_590 Shared Packet RAM for multiple Link Layer usage. 0x49C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_591 Shared Packet RAM for multiple Link Layer usage. 0x49E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_592 Shared Packet RAM for multiple Link Layer usage. 0x4A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_593 Shared Packet RAM for multiple Link Layer usage. 0x4A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_594 Shared Packet RAM for multiple Link Layer usage. 0x4A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_595 Shared Packet RAM for multiple Link Layer usage. 0x4A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_596 Shared Packet RAM for multiple Link Layer usage. 0x4A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_597 Shared Packet RAM for multiple Link Layer usage. 0x4AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_598 Shared Packet RAM for multiple Link Layer usage. 0x4AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_599 Shared Packet RAM for multiple Link Layer usage. 0x4AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_6 Shared Packet RAM for multiple Link Layer usage. 0xC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_60 Shared Packet RAM for multiple Link Layer usage. 0x78 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_600 Shared Packet RAM for multiple Link Layer usage. 0x4B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_601 Shared Packet RAM for multiple Link Layer usage. 0x4B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_602 Shared Packet RAM for multiple Link Layer usage. 0x4B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_603 Shared Packet RAM for multiple Link Layer usage. 0x4B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_604 Shared Packet RAM for multiple Link Layer usage. 0x4B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_605 Shared Packet RAM for multiple Link Layer usage. 0x4BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_606 Shared Packet RAM for multiple Link Layer usage. 0x4BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_607 Shared Packet RAM for multiple Link Layer usage. 0x4BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_608 Shared Packet RAM for multiple Link Layer usage. 0x4C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_609 Shared Packet RAM for multiple Link Layer usage. 0x4C2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_61 Shared Packet RAM for multiple Link Layer usage. 0x7A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_610 Shared Packet RAM for multiple Link Layer usage. 0x4C4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_611 Shared Packet RAM for multiple Link Layer usage. 0x4C6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_612 Shared Packet RAM for multiple Link Layer usage. 0x4C8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_613 Shared Packet RAM for multiple Link Layer usage. 0x4CA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_614 Shared Packet RAM for multiple Link Layer usage. 0x4CC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_615 Shared Packet RAM for multiple Link Layer usage. 0x4CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_616 Shared Packet RAM for multiple Link Layer usage. 0x4D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_617 Shared Packet RAM for multiple Link Layer usage. 0x4D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_618 Shared Packet RAM for multiple Link Layer usage. 0x4D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_619 Shared Packet RAM for multiple Link Layer usage. 0x4D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_62 Shared Packet RAM for multiple Link Layer usage. 0x7C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_620 Shared Packet RAM for multiple Link Layer usage. 0x4D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_621 Shared Packet RAM for multiple Link Layer usage. 0x4DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_622 Shared Packet RAM for multiple Link Layer usage. 0x4DC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_623 Shared Packet RAM for multiple Link Layer usage. 0x4DE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_624 Shared Packet RAM for multiple Link Layer usage. 0x4E0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_625 Shared Packet RAM for multiple Link Layer usage. 0x4E2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_626 Shared Packet RAM for multiple Link Layer usage. 0x4E4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_627 Shared Packet RAM for multiple Link Layer usage. 0x4E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_628 Shared Packet RAM for multiple Link Layer usage. 0x4E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_629 Shared Packet RAM for multiple Link Layer usage. 0x4EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_63 Shared Packet RAM for multiple Link Layer usage. 0x7E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_630 Shared Packet RAM for multiple Link Layer usage. 0x4EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_631 Shared Packet RAM for multiple Link Layer usage. 0x4EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_632 Shared Packet RAM for multiple Link Layer usage. 0x4F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_633 Shared Packet RAM for multiple Link Layer usage. 0x4F2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_634 Shared Packet RAM for multiple Link Layer usage. 0x4F4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_635 Shared Packet RAM for multiple Link Layer usage. 0x4F6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_636 Shared Packet RAM for multiple Link Layer usage. 0x4F8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_637 Shared Packet RAM for multiple Link Layer usage. 0x4FA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_638 Shared Packet RAM for multiple Link Layer usage. 0x4FC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_639 Shared Packet RAM for multiple Link Layer usage. 0x4FE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_64 Shared Packet RAM for multiple Link Layer usage. 0x80 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_640 Shared Packet RAM for multiple Link Layer usage. 0x500 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_641 Shared Packet RAM for multiple Link Layer usage. 0x502 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_642 Shared Packet RAM for multiple Link Layer usage. 0x504 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_643 Shared Packet RAM for multiple Link Layer usage. 0x506 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_644 Shared Packet RAM for multiple Link Layer usage. 0x508 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_645 Shared Packet RAM for multiple Link Layer usage. 0x50A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_646 Shared Packet RAM for multiple Link Layer usage. 0x50C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_647 Shared Packet RAM for multiple Link Layer usage. 0x50E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_648 Shared Packet RAM for multiple Link Layer usage. 0x510 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_649 Shared Packet RAM for multiple Link Layer usage. 0x512 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_65 Shared Packet RAM for multiple Link Layer usage. 0x82 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_650 Shared Packet RAM for multiple Link Layer usage. 0x514 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_651 Shared Packet RAM for multiple Link Layer usage. 0x516 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_652 Shared Packet RAM for multiple Link Layer usage. 0x518 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_653 Shared Packet RAM for multiple Link Layer usage. 0x51A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_654 Shared Packet RAM for multiple Link Layer usage. 0x51C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_655 Shared Packet RAM for multiple Link Layer usage. 0x51E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_656 Shared Packet RAM for multiple Link Layer usage. 0x520 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_657 Shared Packet RAM for multiple Link Layer usage. 0x522 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_658 Shared Packet RAM for multiple Link Layer usage. 0x524 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_659 Shared Packet RAM for multiple Link Layer usage. 0x526 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_66 Shared Packet RAM for multiple Link Layer usage. 0x84 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_660 Shared Packet RAM for multiple Link Layer usage. 0x528 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_661 Shared Packet RAM for multiple Link Layer usage. 0x52A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_662 Shared Packet RAM for multiple Link Layer usage. 0x52C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_663 Shared Packet RAM for multiple Link Layer usage. 0x52E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_664 Shared Packet RAM for multiple Link Layer usage. 0x530 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_665 Shared Packet RAM for multiple Link Layer usage. 0x532 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_666 Shared Packet RAM for multiple Link Layer usage. 0x534 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_667 Shared Packet RAM for multiple Link Layer usage. 0x536 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_668 Shared Packet RAM for multiple Link Layer usage. 0x538 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_669 Shared Packet RAM for multiple Link Layer usage. 0x53A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_67 Shared Packet RAM for multiple Link Layer usage. 0x86 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_670 Shared Packet RAM for multiple Link Layer usage. 0x53C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_671 Shared Packet RAM for multiple Link Layer usage. 0x53E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_672 Shared Packet RAM for multiple Link Layer usage. 0x540 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_673 Shared Packet RAM for multiple Link Layer usage. 0x542 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_674 Shared Packet RAM for multiple Link Layer usage. 0x544 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_675 Shared Packet RAM for multiple Link Layer usage. 0x546 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_676 Shared Packet RAM for multiple Link Layer usage. 0x548 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_677 Shared Packet RAM for multiple Link Layer usage. 0x54A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_678 Shared Packet RAM for multiple Link Layer usage. 0x54C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_679 Shared Packet RAM for multiple Link Layer usage. 0x54E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_68 Shared Packet RAM for multiple Link Layer usage. 0x88 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_680 Shared Packet RAM for multiple Link Layer usage. 0x550 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_681 Shared Packet RAM for multiple Link Layer usage. 0x552 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_682 Shared Packet RAM for multiple Link Layer usage. 0x554 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_683 Shared Packet RAM for multiple Link Layer usage. 0x556 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_684 Shared Packet RAM for multiple Link Layer usage. 0x558 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_685 Shared Packet RAM for multiple Link Layer usage. 0x55A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_686 Shared Packet RAM for multiple Link Layer usage. 0x55C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_687 Shared Packet RAM for multiple Link Layer usage. 0x55E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_688 Shared Packet RAM for multiple Link Layer usage. 0x560 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_689 Shared Packet RAM for multiple Link Layer usage. 0x562 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_69 Shared Packet RAM for multiple Link Layer usage. 0x8A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_690 Shared Packet RAM for multiple Link Layer usage. 0x564 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_691 Shared Packet RAM for multiple Link Layer usage. 0x566 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_692 Shared Packet RAM for multiple Link Layer usage. 0x568 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_693 Shared Packet RAM for multiple Link Layer usage. 0x56A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_694 Shared Packet RAM for multiple Link Layer usage. 0x56C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_695 Shared Packet RAM for multiple Link Layer usage. 0x56E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_696 Shared Packet RAM for multiple Link Layer usage. 0x570 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_697 Shared Packet RAM for multiple Link Layer usage. 0x572 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_698 Shared Packet RAM for multiple Link Layer usage. 0x574 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_699 Shared Packet RAM for multiple Link Layer usage. 0x576 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_7 Shared Packet RAM for multiple Link Layer usage. 0xE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_70 Shared Packet RAM for multiple Link Layer usage. 0x8C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_700 Shared Packet RAM for multiple Link Layer usage. 0x578 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_701 Shared Packet RAM for multiple Link Layer usage. 0x57A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_702 Shared Packet RAM for multiple Link Layer usage. 0x57C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_703 Shared Packet RAM for multiple Link Layer usage. 0x57E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_704 Shared Packet RAM for multiple Link Layer usage. 0x580 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_705 Shared Packet RAM for multiple Link Layer usage. 0x582 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_706 Shared Packet RAM for multiple Link Layer usage. 0x584 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_707 Shared Packet RAM for multiple Link Layer usage. 0x586 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_708 Shared Packet RAM for multiple Link Layer usage. 0x588 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_709 Shared Packet RAM for multiple Link Layer usage. 0x58A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_71 Shared Packet RAM for multiple Link Layer usage. 0x8E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_710 Shared Packet RAM for multiple Link Layer usage. 0x58C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_711 Shared Packet RAM for multiple Link Layer usage. 0x58E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_712 Shared Packet RAM for multiple Link Layer usage. 0x590 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_713 Shared Packet RAM for multiple Link Layer usage. 0x592 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_714 Shared Packet RAM for multiple Link Layer usage. 0x594 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_715 Shared Packet RAM for multiple Link Layer usage. 0x596 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_716 Shared Packet RAM for multiple Link Layer usage. 0x598 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_717 Shared Packet RAM for multiple Link Layer usage. 0x59A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_718 Shared Packet RAM for multiple Link Layer usage. 0x59C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_719 Shared Packet RAM for multiple Link Layer usage. 0x59E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_72 Shared Packet RAM for multiple Link Layer usage. 0x90 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_720 Shared Packet RAM for multiple Link Layer usage. 0x5A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_721 Shared Packet RAM for multiple Link Layer usage. 0x5A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_722 Shared Packet RAM for multiple Link Layer usage. 0x5A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_723 Shared Packet RAM for multiple Link Layer usage. 0x5A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_724 Shared Packet RAM for multiple Link Layer usage. 0x5A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_725 Shared Packet RAM for multiple Link Layer usage. 0x5AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_726 Shared Packet RAM for multiple Link Layer usage. 0x5AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_727 Shared Packet RAM for multiple Link Layer usage. 0x5AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_728 Shared Packet RAM for multiple Link Layer usage. 0x5B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_729 Shared Packet RAM for multiple Link Layer usage. 0x5B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_73 Shared Packet RAM for multiple Link Layer usage. 0x92 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_730 Shared Packet RAM for multiple Link Layer usage. 0x5B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_731 Shared Packet RAM for multiple Link Layer usage. 0x5B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_732 Shared Packet RAM for multiple Link Layer usage. 0x5B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_733 Shared Packet RAM for multiple Link Layer usage. 0x5BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_734 Shared Packet RAM for multiple Link Layer usage. 0x5BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_735 Shared Packet RAM for multiple Link Layer usage. 0x5BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_736 Shared Packet RAM for multiple Link Layer usage. 0x5C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_737 Shared Packet RAM for multiple Link Layer usage. 0x5C2 16 read-write n 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Packet RAM for multiple Link Layer usage. 0x5CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_744 Shared Packet RAM for multiple Link Layer usage. 0x5D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_745 Shared Packet RAM for multiple Link Layer usage. 0x5D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_746 Shared Packet RAM for multiple Link Layer usage. 0x5D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_747 Shared Packet RAM for multiple Link Layer usage. 0x5D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_748 Shared Packet RAM for multiple Link Layer usage. 0x5D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_749 Shared Packet RAM for multiple Link Layer usage. 0x5DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 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Link Layer usage. 0x5E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_756 Shared Packet RAM for multiple Link Layer usage. 0x5E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_757 Shared Packet RAM for multiple Link Layer usage. 0x5EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_758 Shared Packet RAM for multiple Link Layer usage. 0x5EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_759 Shared Packet RAM for multiple Link Layer usage. 0x5EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_76 Shared Packet RAM for multiple Link Layer usage. 0x98 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_760 Shared Packet RAM for multiple Link Layer usage. 0x5F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 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0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_78 Shared Packet RAM for multiple Link Layer usage. 0x9C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_780 Shared Packet RAM for multiple Link Layer usage. 0x618 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_781 Shared Packet RAM for multiple Link Layer usage. 0x61A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_782 Shared Packet RAM for multiple Link Layer usage. 0x61C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_783 Shared Packet RAM for multiple Link Layer usage. 0x61E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_784 Shared Packet RAM for multiple Link Layer usage. 0x620 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_785 Shared Packet RAM for multiple Link Layer usage. 0x622 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_786 Shared Packet RAM for multiple Link Layer usage. 0x624 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_787 Shared Packet RAM for multiple Link Layer usage. 0x626 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_788 Shared Packet RAM for multiple Link Layer usage. 0x628 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_789 Shared Packet RAM for multiple Link Layer usage. 0x62A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_79 Shared Packet RAM for multiple Link Layer usage. 0x9E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_790 Shared Packet RAM for multiple Link Layer usage. 0x62C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_791 Shared Packet RAM for multiple Link Layer usage. 0x62E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_792 Shared Packet RAM for multiple Link Layer usage. 0x630 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_793 Shared Packet RAM for multiple Link Layer usage. 0x632 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_794 Shared Packet RAM for multiple Link Layer usage. 0x634 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_795 Shared Packet RAM for multiple Link Layer usage. 0x636 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_796 Shared Packet RAM for multiple Link Layer usage. 0x638 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_797 Shared Packet RAM for multiple Link Layer usage. 0x63A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_798 Shared Packet RAM for multiple Link Layer usage. 0x63C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_799 Shared Packet RAM for multiple Link Layer usage. 0x63E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_8 Shared Packet RAM for multiple Link Layer usage. 0x10 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_80 Shared Packet RAM for multiple Link Layer usage. 0xA0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_800 Shared Packet RAM for multiple Link Layer usage. 0x640 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_801 Shared Packet RAM for multiple Link Layer usage. 0x642 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_802 Shared Packet RAM for multiple Link Layer usage. 0x644 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_803 Shared Packet RAM for multiple Link Layer usage. 0x646 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_804 Shared Packet RAM for multiple Link Layer usage. 0x648 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_805 Shared Packet RAM for multiple Link Layer usage. 0x64A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_806 Shared Packet RAM for multiple Link Layer usage. 0x64C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_807 Shared Packet RAM for multiple Link Layer usage. 0x64E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_808 Shared Packet RAM for multiple Link Layer usage. 0x650 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_809 Shared Packet RAM for multiple Link Layer usage. 0x652 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_81 Shared Packet RAM for multiple Link Layer usage. 0xA2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_810 Shared Packet RAM for multiple Link Layer usage. 0x654 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_811 Shared Packet RAM for multiple Link Layer usage. 0x656 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_812 Shared Packet RAM for multiple Link Layer usage. 0x658 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_813 Shared Packet RAM for multiple Link Layer usage. 0x65A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_814 Shared Packet RAM for multiple Link Layer usage. 0x65C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_815 Shared Packet RAM for multiple Link Layer usage. 0x65E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_816 Shared Packet RAM for multiple Link Layer usage. 0x660 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_817 Shared Packet RAM for multiple Link Layer usage. 0x662 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_818 Shared Packet RAM for multiple Link Layer usage. 0x664 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_819 Shared Packet RAM for multiple Link Layer usage. 0x666 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_82 Shared Packet RAM for multiple Link Layer usage. 0xA4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_820 Shared Packet RAM for multiple Link Layer usage. 0x668 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_821 Shared Packet RAM for multiple Link Layer usage. 0x66A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_822 Shared Packet RAM for multiple Link Layer usage. 0x66C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_823 Shared Packet RAM for multiple Link Layer usage. 0x66E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_824 Shared Packet RAM for multiple Link Layer usage. 0x670 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_825 Shared Packet RAM for multiple Link Layer usage. 0x672 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_826 Shared Packet RAM for multiple Link Layer usage. 0x674 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_827 Shared Packet RAM for multiple Link Layer usage. 0x676 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_828 Shared Packet RAM for multiple Link Layer usage. 0x678 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_829 Shared Packet RAM for multiple Link Layer usage. 0x67A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_83 Shared Packet RAM for multiple Link Layer usage. 0xA6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_830 Shared Packet RAM for multiple Link Layer usage. 0x67C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_831 Shared Packet RAM for multiple Link Layer usage. 0x67E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_832 Shared Packet RAM for multiple Link Layer usage. 0x680 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_833 Shared Packet RAM for multiple Link Layer usage. 0x682 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_834 Shared Packet RAM for multiple Link Layer usage. 0x684 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_835 Shared Packet RAM for multiple Link Layer usage. 0x686 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_836 Shared Packet RAM for multiple Link Layer usage. 0x688 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_837 Shared Packet RAM for multiple Link Layer usage. 0x68A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_838 Shared Packet RAM for multiple Link Layer usage. 0x68C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_839 Shared Packet RAM for multiple Link Layer usage. 0x68E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_84 Shared Packet RAM for multiple Link Layer usage. 0xA8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_840 Shared Packet RAM for multiple Link Layer usage. 0x690 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_841 Shared Packet RAM for multiple Link Layer usage. 0x692 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_842 Shared Packet RAM for multiple Link Layer usage. 0x694 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_843 Shared Packet RAM for multiple Link Layer usage. 0x696 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_844 Shared Packet RAM for multiple Link Layer usage. 0x698 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_845 Shared Packet RAM for multiple Link Layer usage. 0x69A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_846 Shared Packet RAM for multiple Link Layer usage. 0x69C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_847 Shared Packet RAM for multiple Link Layer usage. 0x69E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_848 Shared Packet RAM for multiple Link Layer usage. 0x6A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_849 Shared Packet RAM for multiple Link Layer usage. 0x6A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_85 Shared Packet RAM for multiple Link Layer usage. 0xAA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_850 Shared Packet RAM for multiple Link Layer usage. 0x6A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_851 Shared Packet RAM for multiple Link Layer usage. 0x6A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_852 Shared Packet RAM for multiple Link Layer usage. 0x6A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_853 Shared Packet RAM for multiple Link Layer usage. 0x6AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_854 Shared Packet RAM for multiple Link Layer usage. 0x6AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_855 Shared Packet RAM for multiple Link Layer usage. 0x6AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_856 Shared Packet RAM for multiple Link Layer usage. 0x6B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_857 Shared Packet RAM for multiple Link Layer usage. 0x6B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_858 Shared Packet RAM for multiple Link Layer usage. 0x6B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_859 Shared Packet RAM for multiple Link Layer usage. 0x6B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_86 Shared Packet RAM for multiple Link Layer usage. 0xAC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_860 Shared Packet RAM for multiple Link Layer usage. 0x6B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_861 Shared Packet RAM for multiple Link Layer usage. 0x6BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_862 Shared Packet RAM for multiple Link Layer usage. 0x6BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_863 Shared Packet RAM for multiple Link Layer usage. 0x6BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_864 Shared Packet RAM for multiple Link Layer usage. 0x6C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_865 Shared Packet RAM for multiple Link Layer usage. 0x6C2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_866 Shared Packet RAM for multiple Link Layer usage. 0x6C4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_867 Shared Packet RAM for multiple Link Layer usage. 0x6C6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_868 Shared Packet RAM for multiple Link Layer usage. 0x6C8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_869 Shared Packet RAM for multiple Link Layer usage. 0x6CA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_87 Shared Packet RAM for multiple Link Layer usage. 0xAE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_870 Shared Packet RAM for multiple Link Layer usage. 0x6CC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_871 Shared Packet RAM for multiple Link Layer usage. 0x6CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_872 Shared Packet RAM for multiple Link Layer usage. 0x6D0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_873 Shared Packet RAM for multiple Link Layer usage. 0x6D2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_874 Shared Packet RAM for multiple Link Layer usage. 0x6D4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_875 Shared Packet RAM for multiple Link Layer usage. 0x6D6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_876 Shared Packet RAM for multiple Link Layer usage. 0x6D8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_877 Shared Packet RAM for multiple Link Layer usage. 0x6DA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_878 Shared Packet RAM for multiple Link Layer usage. 0x6DC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_879 Shared Packet RAM for multiple Link Layer usage. 0x6DE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_88 Shared Packet RAM for multiple Link Layer usage. 0xB0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_880 Shared Packet RAM for multiple Link Layer usage. 0x6E0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_881 Shared Packet RAM for multiple Link Layer usage. 0x6E2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_882 Shared Packet RAM for multiple Link Layer usage. 0x6E4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_883 Shared Packet RAM for multiple Link Layer usage. 0x6E6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_884 Shared Packet RAM for multiple Link Layer usage. 0x6E8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_885 Shared Packet RAM for multiple Link Layer usage. 0x6EA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_886 Shared Packet RAM for multiple Link Layer usage. 0x6EC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_887 Shared Packet RAM for multiple Link Layer usage. 0x6EE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_888 Shared Packet RAM for multiple Link Layer usage. 0x6F0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_889 Shared Packet RAM for multiple Link Layer usage. 0x6F2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_89 Shared Packet RAM for multiple Link Layer usage. 0xB2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_890 Shared Packet RAM for multiple Link Layer usage. 0x6F4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_891 Shared Packet RAM for multiple Link Layer usage. 0x6F6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_892 Shared Packet RAM for multiple Link Layer usage. 0x6F8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_893 Shared Packet RAM for multiple Link Layer usage. 0x6FA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_894 Shared Packet RAM for multiple Link Layer usage. 0x6FC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_895 Shared Packet RAM for multiple Link Layer usage. 0x6FE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_896 Shared Packet RAM for multiple Link Layer usage. 0x700 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_897 Shared Packet RAM for multiple Link Layer usage. 0x702 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_898 Shared Packet RAM for multiple Link Layer usage. 0x704 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_899 Shared Packet RAM for multiple Link Layer usage. 0x706 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_9 Shared Packet RAM for multiple Link Layer usage. 0x12 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_90 Shared Packet RAM for multiple Link Layer usage. 0xB4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_900 Shared Packet RAM for multiple Link Layer usage. 0x708 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_901 Shared Packet RAM for multiple Link Layer usage. 0x70A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_902 Shared Packet RAM for multiple Link Layer usage. 0x70C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_903 Shared Packet RAM for multiple Link Layer usage. 0x70E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_904 Shared Packet RAM for multiple Link Layer usage. 0x710 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_905 Shared Packet RAM for multiple Link Layer usage. 0x712 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_906 Shared Packet RAM for multiple Link Layer usage. 0x714 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_907 Shared Packet RAM for multiple Link Layer usage. 0x716 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_908 Shared Packet RAM for multiple Link Layer usage. 0x718 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_909 Shared Packet RAM for multiple Link Layer usage. 0x71A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_91 Shared Packet RAM for multiple Link Layer usage. 0xB6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_910 Shared Packet RAM for multiple Link Layer usage. 0x71C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_911 Shared Packet RAM for multiple Link Layer usage. 0x71E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_912 Shared Packet RAM for multiple Link Layer usage. 0x720 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_913 Shared Packet RAM for multiple Link Layer usage. 0x722 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_914 Shared Packet RAM for multiple Link Layer usage. 0x724 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_915 Shared Packet RAM for multiple Link Layer usage. 0x726 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_916 Shared Packet RAM for multiple Link Layer usage. 0x728 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_917 Shared Packet RAM for multiple Link Layer usage. 0x72A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_918 Shared Packet RAM for multiple Link Layer usage. 0x72C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_919 Shared Packet RAM for multiple Link Layer usage. 0x72E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_92 Shared Packet RAM for multiple Link Layer usage. 0xB8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_920 Shared Packet RAM for multiple Link Layer usage. 0x730 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_921 Shared Packet RAM for multiple Link Layer usage. 0x732 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_922 Shared Packet RAM for multiple Link Layer usage. 0x734 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_923 Shared Packet RAM for multiple Link Layer usage. 0x736 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_924 Shared Packet RAM for multiple Link Layer usage. 0x738 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_925 Shared Packet RAM for multiple Link Layer usage. 0x73A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_926 Shared Packet RAM for multiple Link Layer usage. 0x73C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_927 Shared Packet RAM for multiple Link Layer usage. 0x73E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_928 Shared Packet RAM for multiple Link Layer usage. 0x740 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_929 Shared Packet RAM for multiple Link Layer usage. 0x742 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_93 Shared Packet RAM for multiple Link Layer usage. 0xBA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_930 Shared Packet RAM for multiple Link Layer usage. 0x744 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_931 Shared Packet RAM for multiple Link Layer usage. 0x746 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_932 Shared Packet RAM for multiple Link Layer usage. 0x748 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_933 Shared Packet RAM for multiple Link Layer usage. 0x74A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_934 Shared Packet RAM for multiple Link Layer usage. 0x74C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_935 Shared Packet RAM for multiple Link Layer usage. 0x74E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_936 Shared Packet RAM for multiple Link Layer usage. 0x750 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_937 Shared Packet RAM for multiple Link Layer usage. 0x752 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_938 Shared Packet RAM for multiple Link Layer usage. 0x754 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_939 Shared Packet RAM for multiple Link Layer usage. 0x756 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_94 Shared Packet RAM for multiple Link Layer usage. 0xBC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_940 Shared Packet RAM for multiple Link Layer usage. 0x758 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_941 Shared Packet RAM for multiple Link Layer usage. 0x75A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_942 Shared Packet RAM for multiple Link Layer usage. 0x75C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_943 Shared Packet RAM for multiple Link Layer usage. 0x75E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_944 Shared Packet RAM for multiple Link Layer usage. 0x760 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_945 Shared Packet RAM for multiple Link Layer usage. 0x762 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_946 Shared Packet RAM for multiple Link Layer usage. 0x764 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_947 Shared Packet RAM for multiple Link Layer usage. 0x766 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_948 Shared Packet RAM for multiple Link Layer usage. 0x768 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_949 Shared Packet RAM for multiple Link Layer usage. 0x76A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_95 Shared Packet RAM for multiple Link Layer usage. 0xBE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_950 Shared Packet RAM for multiple Link Layer usage. 0x76C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_951 Shared Packet RAM for multiple Link Layer usage. 0x76E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_952 Shared Packet RAM for multiple Link Layer usage. 0x770 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_953 Shared Packet RAM for multiple Link Layer usage. 0x772 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_954 Shared Packet RAM for multiple Link Layer usage. 0x774 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_955 Shared Packet RAM for multiple Link Layer usage. 0x776 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_956 Shared Packet RAM for multiple Link Layer usage. 0x778 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_957 Shared Packet RAM for multiple Link Layer usage. 0x77A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_958 Shared Packet RAM for multiple Link Layer usage. 0x77C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_959 Shared Packet RAM for multiple Link Layer usage. 0x77E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_96 Shared Packet RAM for multiple Link Layer usage. 0xC0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_960 Shared Packet RAM for multiple Link Layer usage. 0x780 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_961 Shared Packet RAM for multiple Link Layer usage. 0x782 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_962 Shared Packet RAM for multiple Link Layer usage. 0x784 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_963 Shared Packet RAM for multiple Link Layer usage. 0x786 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_964 Shared Packet RAM for multiple Link Layer usage. 0x788 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_965 Shared Packet RAM for multiple Link Layer usage. 0x78A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_966 Shared Packet RAM for multiple Link Layer usage. 0x78C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_967 Shared Packet RAM for multiple Link Layer usage. 0x78E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_968 Shared Packet RAM for multiple Link Layer usage. 0x790 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_969 Shared Packet RAM for multiple Link Layer usage. 0x792 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_97 Shared Packet RAM for multiple Link Layer usage. 0xC2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_970 Shared Packet RAM for multiple Link Layer usage. 0x794 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_971 Shared Packet RAM for multiple Link Layer usage. 0x796 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_972 Shared Packet RAM for multiple Link Layer usage. 0x798 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_973 Shared Packet RAM for multiple Link Layer usage. 0x79A 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_974 Shared Packet RAM for multiple Link Layer usage. 0x79C 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_975 Shared Packet RAM for multiple Link Layer usage. 0x79E 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_976 Shared Packet RAM for multiple Link Layer usage. 0x7A0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_977 Shared Packet RAM for multiple Link Layer usage. 0x7A2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_978 Shared Packet RAM for multiple Link Layer usage. 0x7A4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_979 Shared Packet RAM for multiple Link Layer usage. 0x7A6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_98 Shared Packet RAM for multiple Link Layer usage. 0xC4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_980 Shared Packet RAM for multiple Link Layer usage. 0x7A8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_981 Shared Packet RAM for multiple Link Layer usage. 0x7AA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_982 Shared Packet RAM for multiple Link Layer usage. 0x7AC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_983 Shared Packet RAM for multiple Link Layer usage. 0x7AE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_984 Shared Packet RAM for multiple Link Layer usage. 0x7B0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_985 Shared Packet RAM for multiple Link Layer usage. 0x7B2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_986 Shared Packet RAM for multiple Link Layer usage. 0x7B4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_987 Shared Packet RAM for multiple Link Layer usage. 0x7B6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_988 Shared Packet RAM for multiple Link Layer usage. 0x7B8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_989 Shared Packet RAM for multiple Link Layer usage. 0x7BA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_99 Shared Packet RAM for multiple Link Layer usage. 0xC6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_990 Shared Packet RAM for multiple Link Layer usage. 0x7BC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_991 Shared Packet RAM for multiple Link Layer usage. 0x7BE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_992 Shared Packet RAM for multiple Link Layer usage. 0x7C0 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_993 Shared Packet RAM for multiple Link Layer usage. 0x7C2 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_994 Shared Packet RAM for multiple Link Layer usage. 0x7C4 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_995 Shared Packet RAM for multiple Link Layer usage. 0x7C6 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_996 Shared Packet RAM for multiple Link Layer usage. 0x7C8 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_997 Shared Packet RAM for multiple Link Layer usage. 0x7CA 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_998 Shared Packet RAM for multiple Link Layer usage. 0x7CC 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write PACKET_RAM_999 Shared Packet RAM for multiple Link Layer usage. 0x7CE 16 read-write n 0x0 0x0 LSBYTE LSBYTE 0 8 read-write MSBYTE MSBYTE 8 8 read-write XCVR_PLL_DIG XCVR_PLL_DIG XCVR_PLL_DIG 0x0 0x0 0x58 registers n CHAN_MAP PLL Channel Mapping 0x8 32 read-write n 0x0 0x0 BMR BLE MBAN Channel Remap 9 1 read-write 0 BLE channel 39 is mapped to BLE channel 39, 2.480 GHz #0 1 BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz #1 BOC BLE Channel Number Override 8 1 read-write 0 BLE channel number comes from the BLE Link Layer #0 1 BLE channel number comes from the CHANNEL_NUM register (BLE protocols 0 and 2) #1 CHANNEL_NUM Protocol specific Channel Number for PLL Frequency Mapping 0 7 read-write HOP_TBL_CFG_OVRD Hop Table Configuration Override 16 3 read-write 010 DFT_PATTERN[15:7] is signed offset to DFT_PATTERN[6:0] mapped channel number #010 011 DFT_PATTERN[15:1] is signed Numerator, DFT_PATTERN[0] is integer selection #011 HOP_TBL_CFG_OVRD_EN Hop Table Configuration Override Enable 19 1 read-write CTUNE_CTRL PLL Coarse Tune Control 0x40 32 read-write n 0x0 0x0 CTUNE_ADJUST Coarse Tune Count Adjustment 16 4 read-write CTUNE_DISABLE Coarse Tune Disable 31 1 read-write CTUNE_MANUAL Manual Coarse Tune Setting 24 7 read-write CTUNE_TARGET_DISABLE Disable Coarse Tune Target 15 1 read-write CTUNE_TARGET_MANUAL Manual Coarse Tune Target 0 12 read-write CTUNE_RES PLL Coarse Tune Results 0x54 32 read-only n 0x0 0x0 CTUNE_BEST_DIFF Coarse Tune Absolute Best Difference 8 8 read-only CTUNE_FREQ_SELECTED Coarse Tune Frequency Selected 16 12 read-only CTUNE_SELECTED Coarse Tune Setting to VCO 0 7 read-only DELAY_MATCH PLL Delay Matching 0x3C 32 read-write n 0x0 0x0 HPM_INTEGER_DELAY High Port Integer Delay Matching 16 4 read-write HPM_SDM_DELAY High Port SDM Delay Matching 8 4 read-write LPM_SDM_DELAY Low Port SDM Delay Matching 0 4 read-write HPM_BUMP PLL HPM Analog Bump Control 0x0 32 read-write n 0x0 0x0 HPM_FDB_RES_CAL rfctrl_tx_dac_bump_fdb_res[1:0] during Calibration 12 2 read-write 00 29 kohms #00 01 58 kohms(gain of 2) #01 10 13 kohms #10 11 23.7 kohms #11 HPM_FDB_RES_TX rfctrl_tx_dac_bump_fdb_res[1:0] during Transmission 8 2 read-write 00 29 kohms #00 01 58 kohms(gain of 2) #01 10 13 kohms #10 11 23.7 kohms #11 HPM_VCM_CAL rfctrl_tx_dac_bump_vcm[2:0] during Calibration 4 3 read-write 000 432 mV #000 001 328 mV #001 010 456 mV #010 011 473 mV #011 100 488 mV #100 101 408 mV #101 110 392 mV #110 111 376 mV #111 HPM_VCM_TX rfctrl_tx_dac_bump_vcm[2:0] during Transmission 0 3 read-write 000 432 mV #000 001 328 mV #001 010 456 mV #010 011 473 mV #011 100 488 mV #100 101 408 mV #101 110 392 mV #110 111 376 mV #111 HPM_CTRL PLL High Port Modulator Control 0x10 32 read-write n 0x0 0x0 HPFF HPM SDM Invalid Flag 13 1 read-write HPM_CAL_INVERT Invert High Port Modulator Calibration 28 1 read-write HPM_DTH_EN Dither Enable for HPM LFSR 23 1 read-write HPM_DTH_SCL HPM Dither Scale 20 1 read-write HPM_INTEGER_INVERT Invert High Port Modulation Integer 27 1 read-write HPM_INTEGER_SCALE High Port Modulation Integer Scale 24 2 read-write 00 No Scaling #00 01 Multiply by 2 #01 10 Divide by 2 #10 HPM_LFSR_SIZE HPM LFSR Length 16 3 read-write 000 LFSR 9, tap mask 100010000 #000 001 LFSR 10, tap mask 1001000000 #001 010 LFSR 11, tap mask 11101000000 #010 011 LFSR 13, tap mask 1101100000000 #011 100 LFSR 15, tap mask 111010000000000 #100 101 LFSR 17, tap mask 11110000000000000 #101 HPM_MOD_IN_INVERT Invert High Port Modulation 31 1 read-write HPM_SDM_IN_DISABLE Disable HPM SDM Input 15 1 read-write HPM_SDM_IN_MANUAL Manual High Port SDM Fractional value 0 10 read-write HPM_SDM_OUT_INVERT Invert HPM SDM Output 14 1 read-write HPM_SDM_RES PLL High Port Sigma Delta Results 0x20 32 read-write n 0x0 0x0 HPM_COUNT_ADJUST HPM_COUNT_ADJUST 28 4 read-write HPM_DENOM High Port Modulator SDM Denominator 16 10 read-write HPM_NUM_SELECTED High Port Modulator SDM Numerator 0 10 read-only LOCK_DETECT PLL Lock Detect Control 0xC 32 read-write n 0x0 0x0 CSFF Cycle Slip Failure Flag, held until cleared 3 1 read-write CS_FAIL Real time status of Cycle Slip circuit 2 1 read-only CTFF CTUNE Failure Flag, held until cleared 1 1 read-write CTUNE_LDF_LEV CTUNE Lock Detect Fail Level 8 4 read-write CT_FAIL Real time status of Coarse Tune Fail signal 0 1 read-only FREQ_COUNT_FINISHED Frequency Meter has finished the Count Time 29 1 read-only FREQ_COUNT_GO Start the Frequency Meter 28 1 read-write FREQ_COUNT_TIME Frequency Meter Count Time 30 2 read-write 00 800 us #00 01 25 us #01 10 50 us #10 11 100 us #11 FTFF Frequency Target Failure Flag 5 1 read-write FTF_RX_THRSH RX Frequency Target Fail Threshold 12 6 read-write FTF_TX_THRSH TX Frequency Target Fail Threshold 20 6 read-write FTW_RX RX Frequency Target Window time select 19 1 read-write 0 4 us #0 1 8 us #1 FTW_TX TX Frequency Target Window time select 27 1 read-write 0 4 us #0 1 8 us #1 FT_FAIL Real time status of Frequency Target Failure 4 1 read-only TAFF TSM Abort Failure Flag 7 1 read-write LPM_CTRL PLL Low Port Modulator Control 0x24 32 read-write n 0x0 0x0 LPFF LPM SDM Invalid Flag 13 1 read-write LPM_DISABLE Disable LPM SDM 15 1 read-write LPM_DTH_SCL LPM Dither Scale 16 4 read-write 0101 -128 to 96 #0101 0110 -256 to 192 #0110 0111 -512 to 384 #0111 1000 -1024 to 768, this is the intended setting for normal operation. #1000 1001 -2048 to 1536 #1001 1010 -4096 to 3072 #1010 1011 -8192 to 6144 #1011 LPM_D_CTRL LPM Dither Control in Override Mode 22 1 read-write LPM_D_OVRD LPM Dither Override Mode Select 23 1 read-write LPM_SCALE LPM Scale Factor 24 4 read-write 0000 No Scaling #0000 0001 Multiply by 2 #0001 0010 Multiply by 4 #0010 0011 Multiply by 8 #0011 0100 Multiply by 16 #0100 0101 Multiply by 32 #0101 0110 Multiply by 64 #0110 0111 Multiply by 128 #0111 1000 Multiply by 256, this is the intended setting for normal operation. #1000 1001 Multiply by 512 #1001 1010 Multiply by 1024 #1010 1011 Multiply by 2048 #1011 LPM_SDM_INV Invert LPM SDM 14 1 read-write LPM_SDM_USE_NEG Use the Negedge of the Sigma Delta clock 31 1 read-write PLL_LD_DISABLE Disable PLL Loop Divider 11 1 read-write PLL_LD_MANUAL Manual PLL Loop Divider value 0 5 read-write LPM_SDM_CTRL1 PLL Low Port Sigma Delta Control 1 0x28 32 read-write n 0x0 0x0 HPM_ARRAY_BIAS Bias value for High Port DAC Array Midpoint 8 7 read-write LPM_INTG Manual Low Port Modulation Integer Value 16 7 read-write LPM_INTG_SELECTED Low Port Modulation Integer Value Selected 0 7 read-only SDM_MAP_DISABLE Disable SDM Mapping 31 1 read-write LPM_SDM_CTRL2 PLL Low Port Sigma Delta Control 2 0x2C 32 read-write n 0x0 0x0 LPM_NUM Low Port Modulation Numerator 0 28 read-write LPM_SDM_CTRL3 PLL Low Port Sigma Delta Control 3 0x30 32 read-write n 0x0 0x0 LPM_DENOM Low Port Modulation Denominator 0 28 read-write LPM_SDM_RES1 PLL Low Port Sigma Delta Result 1 0x34 32 read-only n 0x0 0x0 LPM_NUM_SELECTED Low Port Modulation Numerator Applied 0 28 read-only LPM_SDM_RES2 PLL Low Port Sigma Delta Result 2 0x38 32 read-only n 0x0 0x0 LPM_DENOM_SELECTED Low Port Modulation Denominator Selected 0 28 read-only MOD_CTRL PLL Modulation Control 0x4 32 read-write n 0x0 0x0 HPM_MOD_DISABLE Disable HPM Modulation 27 1 read-write HPM_MOD_MANUAL Manual HPM Modulation 16 8 read-write HPM_SDM_OUT_DISABLE Disable HPM SDM out 31 1 read-write HPM_SDM_OUT_MANUAL Manual HPM SDM out 28 2 read-write MODULATION_WORD_MANUAL Manual Modulation Word 0 13 read-write MOD_DISABLE Disable Modulation Word 15 1 read-write XCVR_RX_DIG XCVR_RX_DIG XCVR_RX_DIG 0x0 0x0 0x1FC registers n AGC_CTRL_0 AGC Control 0 0x4 32 read-write n 0x0 0x0 AGC_DOWN_BBA_STEP_SZ AGC_DOWN_BBA_STEP_SZ 8 4 read-write AGC_DOWN_LNA_STEP_SZ AGC_DOWN_LNA_STEP_SZ 12 4 read-write AGC_DOWN_RSSI_THRESH AGC DOWN RSSI Threshold 24 8 read-write AGC_FREEZE_EN AGC Freeze Enable 3 1 read-write AGC_FREEZE_PRE_OR_AA AGC Freeze Source Selection 4 1 read-write 0 Access Address match (for active protocol) #0 1 Preamble Detect (for active protocol) #1 AGC_UP_EN AGC Up Enable 6 1 read-write AGC_UP_RSSI_THRESH AGC UP RSSI Threshold 16 8 read-write AGC_UP_SRC AGC Up Source 7 1 read-write 0 PDET LO #0 1 RSSI #1 SLOW_AGC_EN Slow AGC Enable 0 1 read-write SLOW_AGC_SRC Slow AGC Source Selection 1 2 read-write 0 Access Address match (for active protocol) #00 1 Preamble Detect (for active protocol) #01 2 Fast AGC expire timer #10 AGC_CTRL_1 AGC Control 1 0x8 32 read-write n 0x0 0x0 BBA_USER_GAIN BBA_USER_GAIN 16 4 read-write LNA_GAIN_SETTLE_TIME LNA_GAIN_SETTLE_TIME 24 8 read-write LNA_USER_GAIN LNA_USER_GAIN 12 4 read-write PDET_HI_SEL_HOLD AGC HOLD hysteresis 23 1 read-write 0 Disabled. #0 1 Enabled. #1 PRESLOW_DOWN_THRESH PRESLOW_DOWN_THRESH 4 4 read-write PRESLOW_EN Pre-slow Enable 22 1 read-write 0 Pre-slow is disabled. #0 1 Pre-slow is enabled. #1 PRESLOW_UP_THRESH PRESLOW_UP_THRESH 0 4 read-write USER_BBA_GAIN_EN User BBA Gain Enable 21 1 read-write USER_LNA_GAIN_EN User LNA Gain Enable 20 1 read-write AGC_CTRL_2 AGC Control 2 0xC 32 read-write n 0x0 0x0 AGC_FAST_EXPIRE AGC Fast Expire 24 6 read-write BBA_GAIN_SETTLE_TIME BBA Gain Settle Time 4 8 read-write BBA_PDET_RST BBA PDET Reset 0 1 read-write BBA_PDET_SEL_HI BBA PDET Threshold High 15 3 read-write 000 0.600V #000 001 0.795V #001 010 0.900V #010 011 0.945V #011 100 1.005V #100 101 1.050V #101 110 1.095V #110 111 1.155V #111 BBA_PDET_SEL_LO BBA PDET Threshold Low 12 3 read-write 000 0.600V #000 001 0.615V #001 010 0.630V #010 011 0.645V #011 100 0.660V #100 101 0.675V #101 110 0.690V #110 111 0.705V #111 LNA_HG_ON_OVR LNA_HG_ON override 31 1 read-write LNA_LG_ON_OVR LNA_LG_ON override 30 1 read-write MAN_PDET_RST MAN PDET Reset 2 1 read-write 0 The peak detector reset signals are controlled automatically by the AGC. #0 1 The BBA_PDET_RST and TZA_PDET_RST are used to manually control the peak detector reset signals. #1 TZA_PDET_RST TZA PDET Reset 1 1 read-write TZA_PDET_SEL_HI TZA PDET Threshold High 21 3 read-write 000 0.600V #000 001 0.645V #001 010 0.705V #010 011 0.750V #011 100 0.795V #100 101 0.855V #101 110 0.900V #110 111 0.945V #111 TZA_PDET_SEL_LO TZA PDET Threshold Low 18 3 read-write 000 0.600V #000 001 0.615V #001 010 0.630V #010 011 0.645V #011 100 0.660V #100 101 0.675V #101 110 0.690V #110 111 0.705V #111 AGC_CTRL_3 AGC Control 3 0x10 32 read-write n 0x0 0x0 AGC_H2S_STEP_SZ AGC_H2S_STEP_SZ 23 5 read-write AGC_PDET_LO_DLY AGC Peak Detect Low Delay 13 3 read-write AGC_RSSI_DELT_H2S AGC_RSSI_DELT_H2S 16 7 read-write AGC_UNFREEZE_TIME AGC Unfreeze Time 0 13 read-write AGC_UP_STEP_SZ AGC Up Step Size 28 4 read-write AGC_GAIN_TBL_03_00 AGC Gain Tables Step 03..00 0x80 32 read-write n 0x0 0x0 BBA_GAIN_00 BBA Gain 00 0 4 read-write BBA_GAIN_01 BBA Gain 01 8 4 read-write BBA_GAIN_02 BBA Gain 02 16 4 read-write BBA_GAIN_03 BBA Gain 03 24 4 read-write LNA_GAIN_00 LNA Gain 00 4 4 read-write LNA_GAIN_01 LNA Gain 01 12 4 read-write LNA_GAIN_02 LNA Gain 02 20 4 read-write LNA_GAIN_03 LNA Gain 03 28 4 read-write AGC_GAIN_TBL_07_04 AGC Gain Tables Step 07..04 0x84 32 read-write n 0x0 0x0 BBA_GAIN_04 BBA Gain 04 0 4 read-write BBA_GAIN_05 BBA Gain 05 8 4 read-write BBA_GAIN_06 BBA Gain 06 16 4 read-write BBA_GAIN_07 BBA Gain 07 24 4 read-write LNA_GAIN_04 LNA Gain 04 4 4 read-write LNA_GAIN_05 LNA Gain 05 12 4 read-write LNA_GAIN_06 LNA Gain 06 20 4 read-write LNA_GAIN_07 LNA Gain 07 28 4 read-write AGC_GAIN_TBL_11_08 AGC Gain Tables Step 11..08 0x88 32 read-write n 0x0 0x0 BBA_GAIN_08 BBA Gain 08 0 4 read-write BBA_GAIN_09 BBA Gain 09 8 4 read-write BBA_GAIN_10 BBA Gain 10 16 4 read-write BBA_GAIN_11 BBA Gain 11 24 4 read-write LNA_GAIN_08 LNA Gain 08 4 4 read-write LNA_GAIN_09 LNA Gain 09 12 4 read-write LNA_GAIN_10 LNA Gain 10 20 4 read-write LNA_GAIN_11 LNA Gain 11 28 4 read-write AGC_GAIN_TBL_15_12 AGC Gain Tables Step 15..12 0x8C 32 read-write n 0x0 0x0 BBA_GAIN_12 BBA Gain 12 0 4 read-write BBA_GAIN_13 BBA Gain 13 8 4 read-write BBA_GAIN_14 BBA Gain 14 16 4 read-write BBA_GAIN_15 BBA Gain 15 24 4 read-write LNA_GAIN_12 LNA Gain 12 4 4 read-write LNA_GAIN_13 LNA Gain 13 12 4 read-write LNA_GAIN_14 LNA Gain 14 20 4 read-write LNA_GAIN_15 LNA Gain 15 28 4 read-write AGC_GAIN_TBL_19_16 AGC Gain Tables Step 19..16 0x90 32 read-write n 0x0 0x0 BBA_GAIN_16 BBA Gain 16 0 4 read-write BBA_GAIN_17 BBA Gain 17 8 4 read-write BBA_GAIN_18 BBA Gain 18 16 4 read-write BBA_GAIN_19 BBA Gain 193 24 4 read-write LNA_GAIN_16 LNA Gain 16 4 4 read-write LNA_GAIN_17 LNA Gain 17 12 4 read-write LNA_GAIN_18 LNA Gain 18 20 4 read-write LNA_GAIN_19 LNA Gain 19 28 4 read-write AGC_GAIN_TBL_23_20 AGC Gain Tables Step 23..20 0x94 32 read-write n 0x0 0x0 BBA_GAIN_20 BBA Gain 20 0 4 read-write BBA_GAIN_21 BBA Gain 21 8 4 read-write BBA_GAIN_22 BBA Gain 22 16 4 read-write BBA_GAIN_23 BBA Gain 23 24 4 read-write LNA_GAIN_20 LNA Gain 20 4 4 read-write LNA_GAIN_21 LNA Gain 21 12 4 read-write LNA_GAIN_22 LNA Gain 22 20 4 read-write LNA_GAIN_23 LNA Gain 23 28 4 read-write AGC_GAIN_TBL_26_24 AGC Gain Tables Step 26..24 0x98 32 read-write n 0x0 0x0 BBA_GAIN_24 BBA Gain 24 0 4 read-write BBA_GAIN_25 BBA Gain 25 8 4 read-write BBA_GAIN_26 BBA Gain 26 16 4 read-write LNA_GAIN_24 LNA Gain 24 4 4 read-write LNA_GAIN_25 LNA Gain 25 12 4 read-write LNA_GAIN_26 LNA Gain 26 20 4 read-write AGC_MAN_AGC_IDX AGC Manual AGC Index 0x1D0 32 read-write n 0x0 0x0 AGC_DCOC_START_PT AGC DCOC Start Point 25 1 read-write AGC_MAN_IDX AGC Manual Index 16 5 read-write AGC_MAN_IDX_EN AGC Manual Index Enable 24 1 read-write AGC_STAT AGC Status 0x14 32 read-only n 0x0 0x0 AGC_FROZEN AGC Frozen Status 9 1 read-only 0 AGC is not frozen. #0 1 AGC is frozen. #1 AGC_IDX_AA_MATCH AGC Gain Index at AA Match 10 5 read-only BBA_PDET_HI_STAT BBA Peak Detector High Status 1 1 read-only BBA_PDET_LO_STAT BBA Peak Detector Low Status 0 1 read-only CURR_AGC_IDX Current AGC Gain Index 4 5 read-only RSSI_ADC_RAW ADC RAW RSSI Reading 16 8 read-only TZA_PDET_HI_STAT TZA Peak Detector High Status 3 1 read-only TZA_PDET_LO_STAT TZA Peak Detector Low Status 2 1 read-only AUXPLL_FCAL_CNT1_0 Aux PLL Frequency Calibration Count 1 and 0 0x1F8 32 read-only n 0x0 0x0 FCAL_COUNT_0 Frequency Calibration Count 0 0 10 read-only FCAL_COUNT_1 Frequency Calibration Count 1 16 10 read-only AUXPLL_FCAL_CNT3_2 Aux PLL Frequency Calibration Count 3 and 2 0x1F4 32 read-only n 0x0 0x0 FCAL_COUNT_2 Aux PLL Frequency Calibration Count 2 0 10 read-only FCAL_COUNT_3 Aux PLL Frequency Calibration Count 3 16 10 read-only AUXPLL_FCAL_CNT5_4 Aux PLL Frequency Calibration Count 5 and 4 0x1F0 32 read-only n 0x0 0x0 FCAL_COUNT_4 Aux PLL Frequency Calibration Count 4 0 10 read-only FCAL_COUNT_5 Aux PLL Frequency Calibration Count 5 16 10 read-only AUXPLL_FCAL_CNT6 Aux PLL Frequency Calibration Count 6 0x1EC 32 read-only n 0x0 0x0 FCAL_BESTDIFF Aux PLL Frequency Calibration Best Difference 16 10 read-only FCAL_COUNT_6 Aux PLL Frequency Calibration Count 6 0 10 read-only AUXPLL_FCAL_CTRL Aux PLL Frequency Calibration Control 0x1E8 32 read-write n 0x0 0x0 AUXPLL_DAC_CAL_ADJUST_DIS Aux PLL Frequency Calibration Disable 7 1 read-write 0 Calibration is enabled #0 1 Calibration is disabled #1 DAC_CAL_ADJUST Aux PLL DAC Calibration Adjust value 16 7 read-only DAC_CAL_ADJUST_MANUAL Aux PLL Frequency DAC Calibration Adjust Manual value 0 7 read-write FCAL_COMP_INV Aux PLL Frequency Calibration Comparison Invert 9 1 read-write 0 (Default) The comparison associated with the count is not inverted. #0 1 The comparison associated with the count is inverted #1 FCAL_RUN_CNT Aux PLL Frequency Calibration Run Count 8 1 read-write 0 Run count is 256 clock cycles #0 1 Run count is 512 clock cycles #1 FCAL_SMP_DLY Aux PLL Frequency Calibration Sample Delay 10 2 read-write 00 The count signal is sampled 1 clk cycle after fcal_run signal is deasserted #00 01 The count signal is sampled 2 clk cycle after fcal_run signal is deasserted #01 10 The count signal is sampled 3 clk cycle after fcal_run signal is deasserted #10 11 The count signal is sampled 4 clk cycle after fcal_run signal is deasserted #11 BBA_RES_TUNE_LIN_VAL_10_8 BBA Resistor Tune Values 10..8 0x7C 32 read-write n 0x0 0x0 BBA_RES_TUNE_LIN_VAL_10 BBA Resistor Tune Linear Gain Step 10 20 10 read-write BBA_RES_TUNE_LIN_VAL_8 BBA Resistor Tune Linear Gain Step 8 0 10 read-write BBA_RES_TUNE_LIN_VAL_9 BBA Resistor Tune Linear Gain Step 9 10 10 read-write BBA_RES_TUNE_LIN_VAL_3_0 BBA Resistor Tune Values 3..0 0x74 32 read-write n 0x0 0x0 BBA_RES_TUNE_LIN_VAL_0 BBA Resistor Tune Linear Gain Step 0 0 8 read-write BBA_RES_TUNE_LIN_VAL_1 BBA Resistor Tune Linear Gain Step 1 8 8 read-write BBA_RES_TUNE_LIN_VAL_2 BBA Resistor Tune Linear Gain Step 2 16 8 read-write BBA_RES_TUNE_LIN_VAL_3 BBA Resistor Tune Linear Gain Step 3 24 8 read-write BBA_RES_TUNE_LIN_VAL_7_4 BBA Resistor Tune Values 7..4 0x78 32 read-write n 0x0 0x0 BBA_RES_TUNE_LIN_VAL_4 BBA Resistor Tune Linear Gain Step 4 0 8 read-write BBA_RES_TUNE_LIN_VAL_5 BBA Resistor Tune Linear Gain Step 5 8 8 read-write BBA_RES_TUNE_LIN_VAL_6 BBA Resistor Tune Linear Gain Step 6 16 8 read-write BBA_RES_TUNE_LIN_VAL_7 BBA Resistor Tune Linear Gain Step 7 24 8 read-write BBA_RES_TUNE_VAL_10_8 BBA Resistor Tune Values 10..8 0x60 32 read-write n 0x0 0x0 BBA_RES_TUNE_VAL_10 BBA Resistor Tune Step 10 8 4 read-write BBA_RES_TUNE_VAL_8 BBA Resistor Tune Step 8 0 4 read-write BBA_RES_TUNE_VAL_9 BBA Resistor Tune Step 9 4 4 read-write BBA_RES_TUNE_VAL_7_0 BBA Resistor Tune Values 7..0 0x5C 32 read-write n 0x0 0x0 BBA_RES_TUNE_VAL_0 BBA Resistor Tune Step 0 0 4 read-write BBA_RES_TUNE_VAL_1 BBA Resistor Tune Step 1 4 4 read-write BBA_RES_TUNE_VAL_2 BBA Resistor Tune Step 2 8 4 read-write BBA_RES_TUNE_VAL_3 BBA Resistor Tune Step 3 12 4 read-write BBA_RES_TUNE_VAL_4 BBA Resistor Tune Step 4 16 4 read-write BBA_RES_TUNE_VAL_5 BBA Resistor Tune Step 5 20 4 read-write BBA_RES_TUNE_VAL_6 BBA Resistor Tune Step 6 24 4 read-write BBA_RES_TUNE_VAL_7 BBA Resistor Tune Step 7 28 4 read-write CCA_ED_LQI_CTRL_0 RX_DIG CCA ED LQI Control Register 0 0x190 32 read-write n 0x0 0x0 CORR_CNTR_THRESH Correlation Count Threshold 8 8 read-write LQI_CNTR LQI Counter 16 8 read-write LQI_CORR_THRESH LQI Correlation Threshold 0 8 read-write SNR_ADJ SNR calculation adjustment 24 6 read-write CCA_ED_LQI_CTRL_1 RX_DIG CCA ED LQI Control Register 1 0x194 32 read-write n 0x0 0x0 CCA1_ED_EN_DIS CCA1_ED_EN Disable 19 1 read-write 0 Normal operation #0 1 CCA1_ED_EN input is disabled #1 LQI_BIAS LQI Bias. 28 4 read-write LQI_RSSI_SENS LQI RSSI Sensitivity 12 4 read-write LQI_RSSI_WEIGHT LQI RSSI Weight 9 3 read-write 0 2.0 #000 1 2.125 #001 2 2.25 #010 3 2.375 #011 4 2.5 #100 5 2.625 #101 6 2.75 #110 7 2.875 #111 MAN_AA_MATCH Manual AA Match 21 1 read-write 0 Normal operation #0 1 Manually asserts the AA match signal for the RX_DIG CCA/ED/LQI and AGC blocks. Intended to be used only for debug. #1 MAN_MEAS_COMPLETE Manual measurement complete 20 1 read-write 0 Normal operation #0 1 Manually asserts the measurement complete signal for the RX_DIG CCA/ED/LQI blocks. Intended to be used only for debug. #1 MEAS_TRANS_TO_IDLE Measurement Transition to IDLE 18 1 read-write 0 Module transitions to RSSI state #0 1 Module transitions to IDLE state #1 RSSI_NOISE_AVG_DELAY RSSI Noise Averaging Delay 0 6 read-write RSSI_NOISE_AVG_FACTOR RSSI Noise Averaging Factor 6 3 read-write 0 1 #000 1 64 #001 2 70 #010 3 128 #011 4 139 #100 5 256 #101 6 277 #110 7 512 #111 SNR_LQI_DIS SNR LQI Disable 16 1 read-write 0 Normal operation. #0 1 The RX_DIG CCA/ED/LQI block ignores the AA match input which starts an LQI measurement. #1 SNR_LQI_WEIGHT SNR LQI Weight 24 4 read-write 0 0.0 #0000 1 1.0 #0001 2 1.125 #0010 3 1.25 #0011 4 1.375 #0100 5 1.5 #0101 6 1.625 #0110 7 1.75 #0111 8 1.875 #1000 9 2.0 #1001 10 2.125 #1010 11 2.25 #1011 12 2.375 #1100 13 2.5 #1101 14 2.625 #1110 15 2.75 #1111 CCA_ED_LQI_STAT_0 RX_DIG CCA ED LQI Status Register 0 0x198 32 read-only n 0x0 0x0 CCA1_STATE CCA1 State 24 1 read-only ED_OUT ED output 8 8 read-only LQI_OUT LQI output 0 8 read-only MEAS_COMPLETE Measurement Complete 25 1 read-only SNR_OUT SNR output 16 8 read-only DCOC_BBA_STEP DCOC BBA DAC Step 0x10C 32 read-write n 0x0 0x0 BBA_DCOC_STEP DCOC BBA Step Size 16 9 read-write BBA_DCOC_STEP_RECIP DCOC BBA Reciprocal of Step Size 0 13 read-write DCOC_CAL1 DCOC Calibration Result 0x180 32 read-only n 0x0 0x0 DCOC_CAL_RES_I DCOC Calibration Result - I Channel 0 12 read-only DCOC_CAL_RES_Q DCOC Calibration Result - Q Channel 16 12 read-only DCOC_CAL2 DCOC Calibration Result 0x184 32 read-only n 0x0 0x0 DCOC_CAL_RES_I DCOC Calibration Result - I Channel 0 12 read-only DCOC_CAL_RES_Q DCOC Calibration Result - Q Channel 16 12 read-only DCOC_CAL3 DCOC Calibration Result 0x188 32 read-only n 0x0 0x0 DCOC_CAL_RES_I DCOC Calibration Result - I Channel 0 12 read-only DCOC_CAL_RES_Q DCOC Calibration Result - Q Channel 16 12 read-only DCOC_CAL_ALPHA DCOC Calibration Alpha 0x168 32 read-only n 0x0 0x0 DCOC_CAL_ALPHA_I DCOC Calibration I-channel ALPHA constant 0 11 read-only DCOC_CAL_ALPHA_Q DCOC_CAL_ALPHA_Q 16 11 read-only DCOC_CAL_BETA_I DCOC Calibration Beta I 0x170 32 read-only n 0x0 0x0 DCOC_CAL_BETA_I DCOC_CAL_BETA_I 0 17 read-only DCOC_CAL_BETA_Q DCOC Calibration Beta Q 0x16C 32 read-only n 0x0 0x0 DCOC_CAL_BETA_Q DCOC_CAL_BETA_Q 0 17 read-only DCOC_CAL_FAIL_TH DCOC Calibration Fail Thresholds 0x160 32 read-write n 0x0 0x0 DCOC_CAL_ALPHA_F_TH DCOC Calibration Alpha Fail Threshold 16 10 read-write DCOC_CAL_BETA_F_TH DCOC Calibration Beta Fail Threshold 0 11 read-write DCOC_CAL_GAIN DCOC Calibration Gain 0x34 32 read-write n 0x0 0x0 DCOC_BBA_CAL_GAIN1 DCOC BBA Calibration Gain 1 8 4 read-write DCOC_BBA_CAL_GAIN2 DCOC BBA Calibration Gain 2 16 4 read-write DCOC_BBA_CAL_GAIN3 DCOC BBA Calibration Gain 3 24 4 read-write DCOC_LNA_CAL_GAIN1 DCOC LNA Calibration Gain 1 12 4 read-write DCOC_LNA_CAL_GAIN2 DCOC LNA Calibration Gain 2 20 4 read-write DCOC_LNA_CAL_GAIN3 DCOC LNA Calibration Gain 3 28 4 read-write DCOC_CAL_GAMMA DCOC Calibration Gamma 0x174 32 read-only n 0x0 0x0 DCOC_CAL_GAMMA_I DCOC_CAL_GAMMA_I 0 16 read-only DCOC_CAL_GAMMA_Q DCOC_CAL_GAMMA_Q 16 16 read-only DCOC_CAL_IIR DCOC Calibration IIR 0x178 32 read-write n 0x0 0x0 DCOC_CAL_IIR1A_IDX DCOC Calibration IIR 1A Index 0 2 read-write 0 1/1 #00 1 1/4 #01 2 1/8 #10 3 1/16 #11 DCOC_CAL_IIR2A_IDX DCOC Calibration IIR 2A Index 2 2 read-write 0 1/1 #00 1 1/4 #01 2 1/8 #10 3 1/16 #11 DCOC_CAL_IIR3A_IDX DCOC Calibration IIR 3A Index 4 2 read-write 0 1/4 #00 1 1/8 #01 2 1/16 #10 3 1/32 #11 DCOC_CAL_PASS_TH DCOC Calibration Pass Thresholds 0x164 32 read-write n 0x0 0x0 DCOC_CAL_ALPHA_P_TH DCOC Calibration Alpha Pass Threshold 16 10 read-write DCOC_CAL_BETA_P_TH DCOC Calibration Beta Pass Threshold 0 11 read-write DCOC_CAL_RCP DCOC Calibration Reciprocals 0x40 32 read-write n 0x0 0x0 ALPHA_CALC_RECIP Alpha Calculation Reciprocal 16 11 read-write DCOC_TMP_CALC_RECIP DCOC Calculation Reciprocal 0 11 read-write DCOC_CTRL_0 DCOC Control 0 0x24 32 read-write n 0x0 0x0 BBA_CORR_POL BBA Correction Polarity 6 1 read-write 0 Normal polarity. #0 1 Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity. #1 DCOC_CAL_CHECK_EN DCOC Calibration Check Enable 15 1 read-write 0 Calibration checking disabled. The DCOC_OFFSET_n registers are always updated during calibration. #0 1 Calibration checking enabled. The DCOC_OFFSET_n registers are updated conditionally depending on the outcome of the pass/fail threshold checks performed on the alpha-hat and beta-hat estimates during calibration. #1 DCOC_CAL_DURATION DCOC Calibration Duration 8 5 read-write DCOC_CORRECT_EN DCOC Correction Enable 4 1 read-write 0 Correction disabled. The DCOC will not correct the DC offset. #0 1 Correction enabled. The DCOC will use the TZA and BBA DACs, and apply digital corrections (if DCOC_CORRECT_SRC=1) to correct the DC offset. #1 DCOC_CORRECT_SRC DCOC Corrector Source 3 1 read-write 0 If correction is enabled, the DCOC will use only the DCOC calibration table to correct the DC offset. #0 1 If correction is enabled, the DCOC will use the DCOC calibration table and then the tracking estimator to correct the DC offset. #1 DCOC_CORR_DLY DCOC Correction Delay 16 5 read-write DCOC_CORR_HOLD_TIME DCOC Correction Hold Time 24 7 read-write 127 The DC correction is not frozen. #1111111 DCOC_MAN DCOC Manual Override 1 1 read-write DCOC_MIDPWR_TRK_DIS DCOC Mid Power Tracking Disable 0 1 read-write 0 Tracking corrections are enabled as determined by DCOC_CORRECT_SRC and DCOC_TRK_MIN_AGC_IDX. #0 1 Tracking corrections are disabled when either the TZA or BBA lo peak detector asserts. #1 DCOC_TRK_EST_OVR Override for the DCOC tracking estimator 2 1 read-write 0 The tracking estimator is enabled only as needed by the corrector #0 1 The tracking estimator remains enabled whenever the DCOC is active #1 TRACK_FROM_ZERO Track from Zero 5 1 read-write 0 Track from current I/Q sample. #0 1 Track from zero. #1 TZA_CORR_POL TZA Correction Polarity 7 1 read-write 0 Normal polarity. #0 1 Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity. #1 DCOC_CTRL_1 DCOC Control 1 0x28 32 read-write n 0x0 0x0 DCOC_ALPHAC_SCALE_GS_IDX DCOC Alpha-C Scaling for Gearshift 18 3 read-write 000 1/2 #000 001 1/4 #001 010 1/8 #010 011 1/16 #011 100 1/32 #100 101 1/64 #101 DCOC_ALPHAC_SCALE_IDX DCOC Alpha-C Scaling 2 3 read-write 000 1/2 #000 001 1/4 #001 010 1/8 #010 011 1/16 #011 100 1/32 #100 101 1/64 #101 DCOC_ALPHA_RADIUS_GS_IDX Alpha-R Scaling for Gearshift 21 3 read-write 000 1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 DCOC_ALPHA_RADIUS_IDX Alpha-R Scaling 5 3 read-write 000 1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 DCOC_SIGN_SCALE_GS_IDX DCOC Sign Scaling for Gearshift 16 2 read-write 00 1/8 #00 01 1/16 #01 10 1/32 #10 11 1/64 #11 DCOC_SIGN_SCALE_IDX DCOC Sign Scaling 0 2 read-write 00 1/8 #00 01 1/16 #01 10 1/32 #10 11 1/64 #11 DCOC_TRK_EST_GS_CNT DCOC Tracking Estimator Gearshift Count 12 3 read-write DCOC_TRK_MIN_AGC_IDX DCOC Tracking Minimum AGC Table Index 24 5 read-write DCOC_DAC_INIT DCOC DAC Initialization 0x2C 32 read-write n 0x0 0x0 BBA_DCOC_INIT_I DCOC BBA Init I 0 6 read-write BBA_DCOC_INIT_Q DCOC BBA Init Q 8 6 read-write TZA_DCOC_INIT_I DCOC TZA Init I 16 8 read-write TZA_DCOC_INIT_Q DCOC TZA Init Q 24 8 read-write DCOC_DC_EST DCOC DC Estimate 0x3C 32 read-only n 0x0 0x0 DC_EST_I DCOC DC Estimate I 0 12 read-only DC_EST_Q DCOC DC Estimate Q 16 12 read-only DCOC_DIG_MAN DCOC Digital Correction Manual Override 0x30 32 read-write n 0x0 0x0 DIG_DCOC_INIT_I DCOC DIG Init I 0 12 read-write DIG_DCOC_INIT_Q DCOC DIG Init Q 16 12 read-write DCOC_OFFSET_0 DCOC Offset 0xA0 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_1 DCOC Offset 0xA4 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_10 DCOC Offset 0xC8 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_11 DCOC Offset 0xCC 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_12 DCOC Offset 0xD0 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_13 DCOC Offset 0xD4 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_14 DCOC Offset 0xD8 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_15 DCOC Offset 0xDC 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_16 DCOC Offset 0xE0 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_17 DCOC Offset 0xE4 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_18 DCOC Offset 0xE8 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_19 DCOC Offset 0xEC 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_2 DCOC Offset 0xA8 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_20 DCOC Offset 0xF0 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_21 DCOC Offset 0xF4 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_22 DCOC Offset 0xF8 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_23 DCOC Offset 0xFC 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_24 DCOC Offset 0x100 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_25 DCOC Offset 0x104 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_26 DCOC Offset 0x108 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_3 DCOC Offset 0xAC 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_4 DCOC Offset 0xB0 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_5 DCOC Offset 0xB4 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_6 DCOC Offset 0xB8 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_7 DCOC Offset 0xBC 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_8 DCOC Offset 0xC0 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_OFFSET_9 DCOC Offset 0xC4 32 read-write n 0x0 0x0 DCOC_BBA_OFFSET_I DCOC BBA I-channel offset 0 6 read-write DCOC_BBA_OFFSET_Q DCOC BBA Q-channel offset 8 6 read-write DCOC_TZA_OFFSET_I DCOC TZA I-channel offset 16 8 read-write DCOC_TZA_OFFSET_Q DCOC TZA Q-channel offset 24 8 read-write DCOC_STAT DCOC Status 0x38 32 read-only n 0x0 0x0 BBA_DCOC_I DCOC BBA DAC I 0 6 read-only BBA_DCOC_Q DCOC BBA DAC Q 8 6 read-only DCOC_CAL_GTWSR DCOC calibration Good Table Written Since Reset 7 1 read-only 0 A Passing calibration result has not occurred since the last radio reset. #0 1 A Passing calibration result has occurred since the last radio reset. #1 DCOC_CAL_RESULT DCOC_CAL_RESULT 14 2 read-only 00 Calibration checks failed. DCOC_OFFSET_n tables not updated. #00 01 Calibration checks neither passed nor failed, DCOC_OFFSET_n tables not updated. #01 10 Calibration checks neither passed nor failed, DCOC_OFFSET_n tables updated since no previous Pass condition has occurred since the last radio reset. #10 11 Calibration checks passed. DCOC_OFFSET_n tables updated #11 TZA_DCOC_I DCOC TZA DAC I 16 8 read-only TZA_DCOC_Q DCOC TZA DAC Q 24 8 read-only DCOC_TZA_STEP_0 DCOC TZA DAC Step 0 0x110 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_0 DCOC_TZA_STEP_GAIN_0 16 12 read-write DCOC_TZA_STEP_RCP_0 DCOC_TZA_STEP_RCP_0 0 13 read-write DCOC_TZA_STEP_1 DCOC TZA DAC Step 1 0x114 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_1 DCOC_TZA_STEP_GAIN_1 16 12 read-write DCOC_TZA_STEP_RCP_1 DCOC_TZA_STEP_RCP_1 0 13 read-write DCOC_TZA_STEP_10 DCOC TZA DAC Step 10 0x138 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_10 DCOC_TZA_STEP_GAIN_10 16 14 read-write DCOC_TZA_STEP_RCP_10 DCOC_TZA_STEP_RCP_10 0 13 read-write DCOC_TZA_STEP_2 DCOC TZA DAC Step 2 0x118 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_2 DCOC_TZA_STEP_GAIN_2 16 12 read-write DCOC_TZA_STEP_RCP_2 DCOC_TZA_STEP_RCP_2 0 13 read-write DCOC_TZA_STEP_3 DCOC TZA DAC Step 3 0x11C 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_3 DCOC_TZA_STEP_GAIN_3 16 12 read-write DCOC_TZA_STEP_RCP_3 DCOC_TZA_STEP_RCP_3 0 13 read-write DCOC_TZA_STEP_4 DCOC TZA DAC Step 4 0x120 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_4 DCOC_TZA_STEP_GAIN_4 16 12 read-write DCOC_TZA_STEP_RCP_4 DCOC_TZA_STEP_RCP_4 0 13 read-write DCOC_TZA_STEP_5 DCOC TZA DAC Step 5 0x124 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_5 DCOC_TZA_STEP_GAIN_5 16 12 read-write DCOC_TZA_STEP_RCP_5 DCOC_TZA_STEP_RCP_5 0 13 read-write DCOC_TZA_STEP_6 DCOC TZA DAC Step 6 0x128 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_6 DCOC_TZA_STEP_GAIN_6 16 12 read-write DCOC_TZA_STEP_RCP_6 DCOC_TZA_STEP_RCP_6 0 13 read-write DCOC_TZA_STEP_7 DCOC TZA DAC Step 7 0x12C 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_7 DCOC_TZA_STEP_GAIN_7 16 13 read-write DCOC_TZA_STEP_RCP_7 DCOC_TZA_STEP_RCP_7 0 13 read-write DCOC_TZA_STEP_8 DCOC TZA DAC Step 5 0x130 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_8 DCOC_TZA_STEP_GAIN_8 16 13 read-write DCOC_TZA_STEP_RCP_8 DCOC_TZA_STEP_RCP_8 0 13 read-write DCOC_TZA_STEP_9 DCOC TZA DAC Step 9 0x134 32 read-write n 0x0 0x0 DCOC_TZA_STEP_GAIN_9 DCOC_TZA_STEP_GAIN_9 16 14 read-write DCOC_TZA_STEP_RCP_9 DCOC_TZA_STEP_RCP_9 0 13 read-write DC_RESID_CTRL DC Residual Control 0x1D4 32 read-write n 0x0 0x0 DC_RESID_ALPHA DC Residual Alpha 12 3 read-write DC_RESID_DLY DC Residual Delay 16 3 read-write DC_RESID_EXT_DC_EN DC Residual External DC Enable 20 1 read-write DC_RESID_ITER_FREEZE DC Residual Iteration Freeze 8 4 read-write DC_RESID_MIN_AGC_IDX DC Residual Minimum AGC Table Index 24 5 read-write DC_RESID_NWIN DC Residual NWIN 0 7 read-write DC_RESID_EST DC Residual Estimate 0x1D8 32 read-only n 0x0 0x0 DC_RESID_OFFSET_I DC Residual Offset I 0 13 read-only DC_RESID_OFFSET_Q DC Residual Offset Q 16 13 read-only IQMC_CAL IQMC Calibration 0x4C 32 read-write n 0x0 0x0 IQMC_GAIN_ADJ IQ Mismatch Correction Gain Coeff 0 11 read-write IQMC_PHASE_ADJ IQ Mismatch Correction Phase Coeff 16 12 read-write IQMC_CTRL IQMC Control 0x48 32 read-write n 0x0 0x0 IQMC_CAL_EN IQ Mismatch Cal Enable 0 1 read-write IQMC_DC_GAIN_ADJ IQ Mismatch Correction DC Gain Coeff 16 11 read-write IQMC_NUM_ITER IQ Mismatch Cal Num Iter 8 8 read-write LNA_GAIN_LIN_VAL_2_0 LNA Linear Gain Values 2..0 0x64 32 read-write n 0x0 0x0 LNA_GAIN_LIN_VAL_0 LNA Linear Gain Step 0 0 10 read-write LNA_GAIN_LIN_VAL_1 LNA Linear Gain Step 1 10 10 read-write LNA_GAIN_LIN_VAL_2 LNA Linear Gain Step 2 20 10 read-write LNA_GAIN_LIN_VAL_5_3 LNA Linear Gain Values 5..3 0x68 32 read-write n 0x0 0x0 LNA_GAIN_LIN_VAL_3 LNA Linear Gain Step 3 0 10 read-write LNA_GAIN_LIN_VAL_4 LNA Linear Gain Step 4 10 10 read-write LNA_GAIN_LIN_VAL_5 LNA Linear Gain Step 5 20 10 read-write LNA_GAIN_LIN_VAL_8_6 LNA Linear Gain Values 8..6 0x6C 32 read-write n 0x0 0x0 LNA_GAIN_LIN_VAL_6 LNA Linear Gain Step 6 0 10 read-write LNA_GAIN_LIN_VAL_7 LNA Linear Gain Step 7 10 10 read-write LNA_GAIN_LIN_VAL_8 LNA Linear Gain Step 8 20 10 read-write LNA_GAIN_LIN_VAL_9 LNA Linear Gain Values 9 0x70 32 read-write n 0x0 0x0 LNA_GAIN_LIN_VAL_9 LNA Linear Gain Step 9 0 10 read-write LNA_GAIN_VAL_3_0 LNA_GAIN Step Values 3..0 0x50 32 read-write n 0x0 0x0 LNA_GAIN_VAL_0 LNA_GAIN step 0 0 8 read-write LNA_GAIN_VAL_1 LNA_GAIN step 1 8 8 read-write LNA_GAIN_VAL_2 LNA_GAIN step 2 16 8 read-write LNA_GAIN_VAL_3 LNA_GAIN step 3 24 8 read-write LNA_GAIN_VAL_7_4 LNA_GAIN Step Values 7..4 0x54 32 read-write n 0x0 0x0 LNA_GAIN_VAL_4 LNA_GAIN step 4 0 8 read-write LNA_GAIN_VAL_5 LNA_GAIN step 5 8 8 read-write LNA_GAIN_VAL_6 LNA_GAIN step 6 16 8 read-write LNA_GAIN_VAL_7 LNA_GAIN step 7 24 8 read-write LNA_GAIN_VAL_8 LNA_GAIN Step Values 8 0x58 32 read-write n 0x0 0x0 LNA_GAIN_VAL_8 LNA_GAIN step 8 0 8 read-write LNA_GAIN_VAL_9 LNA_GAIN step 9 8 8 read-write RSSI_CTRL_0 RSSI Control 0 0x18 32 read-write n 0x0 0x0 RSSI_ADJ RSSI Adjustment 24 8 read-write RSSI_HOLD_DELAY RSSI Hold Delay 10 6 read-write RSSI_HOLD_EN RSSI Hold Enable 3 1 read-write RSSI_HOLD_SRC RSSI Hold Source Selection 1 2 read-write 00 Access Address match #00 01 Preamble Detect #01 RSSI_IIR_CW_WEIGHT RSSI IIR CW Weighting 5 2 read-write 0 Bypass #00 1 1/8 #01 2 1/16 #10 3 1/32 #11 RSSI_IIR_WEIGHT RSSI IIR Weighting 16 4 read-write 0 Bypass #0000 1 1/2 #0001 2 1/4 #0010 3 1/8 #0011 4 1/16 #0100 5 1/32 #0101 RSSI_N_WINDOW_NB RSSI N Window Average Narrowband 7 3 read-write 0 No averaging #000 1 Averaging window length is 2 samples #001 2 Averaging window length is 4 samples #010 3 Averaging window length is 8 samples #011 4 Averaging window length is 16 samples #100 5 Averaging window length is 32 samples #101 RSSI_USE_VALS RSSI Values Selection 0 1 read-write RSSI_VLD_SETTLE RSSI Valid Settle 20 3 read-write RSSI_CTRL_1 RSSI Control 1 0x1C 32 read-only n 0x0 0x0 RSSI_OUT RSSI Reading 24 8 read-only RX_CHF_COEF_0 Receive Channel Filter Coefficient 0 0x1A0 32 read-write n 0x0 0x0 RX_CH_FILT_H0 RX Channel Filter Coefficient 0 0 6 read-write RX_CHF_COEF_1 Receive Channel Filter Coefficient 1 0x1A4 32 read-write n 0x0 0x0 RX_CH_FILT_H1 RX Channel Filter Coefficient 1 0 6 read-write RX_CHF_COEF_10 Receive Channel Filter Coefficient 10 0x1C8 32 read-write n 0x0 0x0 RX_CH_FILT_H10 RX Channel Filter Coefficient 10 0 10 read-write RX_CHF_COEF_11 Receive Channel Filter Coefficient 11 0x1CC 32 read-write n 0x0 0x0 RX_CH_FILT_H11 RX Channel Filter Coefficient 11 0 10 read-write RX_CHF_COEF_2 Receive Channel Filter Coefficient 2 0x1A8 32 read-write n 0x0 0x0 RX_CH_FILT_H2 RX Channel Filter Coefficient 2 0 7 read-write RX_CHF_COEF_3 Receive Channel Filter Coefficient 3 0x1AC 32 read-write n 0x0 0x0 RX_CH_FILT_H3 RX Channel Filter Coefficient 3 0 7 read-write RX_CHF_COEF_4 Receive Channel Filter Coefficient 4 0x1B0 32 read-write n 0x0 0x0 RX_CH_FILT_H4 RX Channel Filter Coefficient 4 0 7 read-write RX_CHF_COEF_5 Receive Channel Filter Coefficient 5 0x1B4 32 read-write n 0x0 0x0 RX_CH_FILT_H5 RX Channel Filter Coefficient 5 0 7 read-write RX_CHF_COEF_6 Receive Channel Filter Coefficient 6 0x1B8 32 read-write n 0x0 0x0 RX_CH_FILT_H6 RX Channel Filter Coefficient 6 0 8 read-write RX_CHF_COEF_7 Receive Channel Filter Coefficient 7 0x1BC 32 read-write n 0x0 0x0 RX_CH_FILT_H7 RX Channel Filter Coefficient 7 0 8 read-write RX_CHF_COEF_8 Receive Channel Filter Coefficient 8 0x1C0 32 read-write n 0x0 0x0 RX_CH_FILT_H8 RX Channel Filter Coefficient 8 0 9 read-write RX_CHF_COEF_9 Receive Channel Filter Coefficient 9 0x1C4 32 read-write n 0x0 0x0 RX_CH_FILT_H9 RX Channel Filter Coefficient 9 0 9 read-write RX_DIG_CTRL RX Digital Control 0x0 32 read-write n 0x0 0x0 RX_ADC_NEGEDGE Receive ADC Negative Edge Selection 0 1 read-write 0 Register ADC data on positive edge of clock #0 1 Register ADC data on negative edge of clock #1 RX_ADC_POL Receive ADC Polarity 3 1 read-write 0 ADC output of 1'b0 maps to -1, 1'b1 maps to +1 (default) #0 1 ADC output of 1'b0 maps to +1, 1'b1 maps to -1 #1 RX_AGC_EN AGC Global Enable 11 1 read-write 0 AGC is disabled. #0 1 AGC is enabled. #1 RX_CH_FILT_BYPASS Receive Channel Filter Bypass 1 1 read-write 0 Channel filter is enabled. #0 1 Disable and bypass channel filter. #1 RX_DCOC_CAL_EN DCOC Calibration Enable 13 1 read-write 0 DCOC calibration is disabled. #0 1 DCOC calibration is enabled. #1 RX_DCOC_EN DCOC Enable 12 1 read-write 0 DCOC is disabled. #0 1 DCOC is enabled. #1 RX_DC_RESID_EN DC Residual Enable 15 1 read-write 0 DC Residual block is disabled. #0 1 DC Residual block is enabled. #1 RX_DEC_FILT_GAIN Decimation Filter Fractional Gain 20 5 read-write RX_DEC_FILT_HAZARD Decimator output, hazard condition detected 28 1 read-only 0 A hazard condition has not been detected #0 1 A hazard condition has been detected #1 RX_DEC_FILT_HZD_CORR_DIS Decimator filter hazard correction disable 25 1 read-write RX_DEC_FILT_OSR Decimation Filter Oversampling 4 3 read-write 0 OSR 4 #000 1 OSR 8 #001 2 OSR 16 #010 3 OSR 6 #011 4 OSR 32 #100 5 OSR 12 #101 6 OSR 24 #110 RX_DEC_FILT_SAT_I Decimator output, saturation detected for I channel 30 1 read-only 0 A saturation condition has not occurred. #0 1 A saturation condition has occurred. #1 RX_DEC_FILT_SAT_Q Decimator output, saturation detected for Q channel 31 1 read-only 0 A saturation condition has not occurred. #0 1 A saturation condition has occurred. #1 RX_DMA_DTEST_EN RX DMA and DTEST enable 18 1 read-write RX_FSK_ZB_SEL Demodulator select 8 1 read-write 0 FSK demodulator. #0 RX_IQ_SWAP RX IQ Swap 14 1 read-write 0 IQ swap is disabled. #0 1 IQ swap is enabled. #1 RX_NORM_EN Normalizer Enable 9 1 read-write 0 Normalizer is disabled. #0 1 Normalizer is enabled. #1 RX_RSSI_EN RSSI Measurement Enable 10 1 read-write 0 RSSI measurement is disabled. #0 1 RSSI measurement is enabled. #1 RX_RSSI_FILT_HAZARD Decimator output for RSSI, hazard condition detected 29 1 read-only 0 A hazard condition has not been detected #0 1 A hazard condition has been detected #1 RX_SRC_EN RX Sample Rate Converter Enable 16 1 read-write 0 SRC is disabled. #0 1 SRC is enabled. #1 RX_SRC_RATE RX Sample Rate Converter Rate Selections 17 1 read-write 0 SRC is configured for a First Order Hold rate of 8/13. #0 1 SRC is configured for a Zero Order Hold rate of 12/13. #1 RX_RCCAL_CTRL0 RX RC Calibration Control0 0x1DC 32 read-write n 0x0 0x0 BBA_RCCAL_DIS BBA RC Calibration Disable 9 1 read-write 0 BBA RC Calibration is enabled #0 1 BBA RC Calibration is disabled #1 BBA_RCCAL_MANUAL BBA RC Calibration manual value 4 5 read-write BBA_RCCAL_OFFSET BBA RC Calibration value offset 0 4 read-write RCCAL_COMP_INV RC Calibration comp_out Invert 15 1 read-write 0 The comp_out signal polarity is NOT inverted #0 1 The comp_out signal polarity is inverted #1 RCCAL_SMP_DLY RC Calibration Sample Delay 12 2 read-write 00 The comp_out signal is sampled 0 clk cycle after sample signal is deasserted #00 01 The comp_out signal is sampled 1 clk cycle after sample signal is deasserted #01 10 The comp_out signal is sampled 2 clk cycle after sample signal is deasserted #10 11 The comp_out signal is sampled 3 clk cycle after sample signal is deasserted #11 TZA_RCCAL_DIS TZA RC Calibration Disable 25 1 read-write 0 TZA RC Calibration is enabled #0 1 TZA RC Calibration is disabled #1 TZA_RCCAL_MANUAL TZA RC Calibration manual value 20 5 read-write TZA_RCCAL_OFFSET TZA RC Calibration value offset 16 4 read-write RX_RCCAL_CTRL1 RX RC Calibration Control1 0x1E0 32 read-write n 0x0 0x0 ADC_RCCAL_DIS ADC RC Calibration Disable 9 1 read-write 0 ADC RC Calibration is enabled #0 1 ADC RC Calibration is disabled #1 ADC_RCCAL_MANUAL ADC RC Calibration manual value 4 5 read-write ADC_RCCAL_OFFSET ADC RC Calibration value offset 0 4 read-write BBA2_RCCAL_DIS BBA2 RC Calibration Disable 25 1 read-write 0 BBA2 RC Calibration is enabled #0 1 BBA2 RC Calibration is disabled #1 BBA2_RCCAL_MANUAL BBA2 RC Calibration manual value 20 5 read-write BBA2_RCCAL_OFFSET BBA2 RC Calibration value offset 16 4 read-write RX_RCCAL_STAT RX RC Calibration Status 0x1E4 32 read-only n 0x0 0x0 ADC_RCCAL ADC RC Calibration 5 5 read-only BBA2_RCCAL BBA2 RC Calibration 10 5 read-only BBA_RCCAL BBA RC Calibration 16 5 read-only RCCAL_CODE RC Calibration code 0 5 read-only TZA_RCCAL TZA RC Calibration 21 5 read-only XCVR_TSM XCVR_TSM XCVR_TSM 0x0 0x0 0x12C registers n CTRL TSM CONTROL 0x0 32 read-write n 0x0 0x0 ABORT_ON_CTUNE Abort On Coarse Tune Lock Detect Failure 18 1 read-write 0 don't allow TSM abort on Coarse Tune Unlock Detect #0 1 allow TSM abort on Coarse Tune Unlock Detect #1 ABORT_ON_CYCLE_SLIP Abort On Cycle Slip Lock Detect Failure 19 1 read-write 0 don't allow TSM abort on Cycle Slip Unlock Detect #0 1 allow TSM abort on Cycle Slip Unlock Detect #1 ABORT_ON_FREQ_TARG Abort On Frequency Target Lock Detect Failure 20 1 read-write 0 don't allow TSM abort on Frequency Target Unlock Detect #0 1 allow TSM abort on Frequency Target Unlock Detect #1 BKPT TSM Breakpoint 24 8 read-write DATA_PADDING_EN Data Padding Enable 6 2 read-write 00 Disable TX Data Padding #00 01 Enable TX Data Padding #01 FORCE_RX_EN Force Receive Enable 3 1 read-write 0 TSM Idle #0 1 TSM executes a RX sequence #1 FORCE_TX_EN Force Transmit Enable 2 1 read-write 0 TSM Idle #0 1 TSM executes a TX sequence #1 PA_RAMP_SEL PA Ramp Selection 4 2 read-write RAMP_DN_DELAY PA Ramp Down Delay 12 4 read-write RX_ABORT_DIS Receive Abort Disable 17 1 read-write TSM_IRQ0_EN TSM_IRQ0 Enable/Disable bit 8 1 read-write 0 TSM_IRQ0 is disabled #0 1 TSM_IRQ0 is enabled #1 TSM_IRQ1_EN TSM_IRQ1 Enable/Disable bit 9 1 read-write 0 TSM_IRQ1 is disabled #0 1 TSM_IRQ1 is enabled #1 TSM_SOFT_RESET TSM Soft Reset 1 1 read-write 0 TSM Soft Reset removed. Normal operation. #0 1 TSM Soft Reset engaged. TSM forced to IDLE, and holds there until the bit is cleared. #1 TX_ABORT_DIS Transmit Abort Disable 16 1 read-write END_OF_SEQ TSM END OF SEQUENCE 0x4 32 read-write n 0x0 0x0 END_OF_RX_WD End of RX Warmdown 24 8 read-write END_OF_RX_WU End of RX Warmup 16 8 read-write END_OF_TX_WD End of TX Warmdown 8 8 read-write END_OF_TX_WU End of TX Warmup 0 8 read-write FAST_CTRL1 TSM FAST WARMUP CONTROL 1 0x28 32 read-write n 0x0 0x0 FAST_RX2TX_EN Fast TSM RX-to-TX Transition Enable 2 1 read-write FAST_RX2TX_START These bits currently have no functionality. 8 8 read-write FAST_RX_WU_EN Fast TSM RX Warmup Enable 1 1 read-write 0 Fast TSM RX Warmups are disabled #0 1 Fast TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup, and for BLE mode, the RF channel is not an advertising channel. #1 FAST_TX_WU_EN Fast TSM TX Warmup Enable 0 1 read-write 0 Fast TSM TX Warmups are disabled #0 1 Fast TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup, and for BLE mode, the RF channel is not an advertising channel. #1 FAST_WU_CLEAR Fast TSM Warmup Clear State 3 1 read-write FAST_CTRL2 TSM FAST WARMUP CONTROL 2 0x2C 32 read-write n 0x0 0x0 FAST_DEST_RX Fast TSM RX Jump-to Point 24 8 read-write FAST_DEST_TX Fast TSM TX Jump-to Point 8 8 read-write FAST_START_RX Fast TSM RX Jump-from Point 16 8 read-write FAST_START_TX Fast TSM TX Jump-from Point 0 8 read-write OVRD0 TSM OVERRIDE REGISTER 0 0x11C 32 read-write n 0x0 0x0 BB_LDO_ADCDAC_EN_OVRD Override value for BB_LDO_ADCDAC_EN 3 1 read-write BB_LDO_ADCDAC_EN_OVRD_EN Override control for BB_LDO_ADCDAC_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_ADCDAC_EN_OVRD to override the signal bb_ldo_adcdac_en . #1 BB_LDO_BBA_EN_OVRD Override value for BB_LDO_BBA_EN 5 1 read-write BB_LDO_BBA_EN_OVRD_EN Override control for BB_LDO_BBA_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_BBA_EN_OVRD to override the signal bb_ldo_bba_en . #1 BB_LDO_FDBK_BLEED_EN_OVRD Override value for BB_LDO_FDBK_BLEED_EN 15 1 read-write BB_LDO_FDBK_BLEED_EN_OVRD_EN Override control for BB_LDO_FDBK_BLEED_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_FDBK_BLEED_EN_OVRD to override the signal bb_ldo_fdbk_bleed_en . #1 BB_LDO_FDBK_EN_OVRD Override value for BB_LDO_FDBK_EN 9 1 read-write BB_LDO_FDBK_EN_OVRD_EN Override control for BB_LDO_FDBK_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_FDBK_EN_OVRD to override the signal bb_ldo_fdbk_en . #1 BB_LDO_HF_EN_OVRD Override value for BB_LDO_HF_EN 1 1 read-write BB_LDO_HF_EN_OVRD_EN Override control for BB_LDO_HF_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_HF_EN_OVRD to override the signal bb_ldo_hf_en . #1 BB_LDO_PD_EN_OVRD Override value for BB_LDO_PD_EN 7 1 read-write BB_LDO_PD_EN_OVRD_EN Override control for BB_LDO_PD_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_PD_EN_OVRD to override the signal bb_ldo_pd_en . #1 BB_LDO_VCOLO_BLEED_EN_OVRD Override value for BB_LDO_VCOLO_BLEED_EN 17 1 read-write BB_LDO_VCOLO_BLEED_EN_OVRD_EN Override control for BB_LDO_VCOLO_BLEED_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VCOLO_BLEED_EN_OVRD to override the signal bb_ldo_vcolo_bleed_en . #1 BB_LDO_VCOLO_EN_OVRD Override value for BB_LDO_VCOLO_EN 11 1 read-write BB_LDO_VCOLO_EN_OVRD_EN Override control for BB_LDO_VCOLO_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VCOLO_EN_OVRD to override the signal bb_ldo_vcolo_en . #1 BB_LDO_VCOLO_FASTCHARGE_EN_OVRD Override value for BB_LDO_VCOLO_FASTCHARGE_EN 19 1 read-write BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN Override control for BB_LDO_VCOLO_FASTCHARGE_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VCOLO_FASTCHARGE_EN_OVRD to override the signal bb_ldo_vcolo_fastcharge_en . #1 BB_LDO_VTREF_EN_OVRD Override value for BB_LDO_VTREF_EN 13 1 read-write BB_LDO_VTREF_EN_OVRD_EN Override control for BB_LDO_VTREF_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of BB_LDO_VTREF_EN_OVRD to override the signal bb_ldo_vtref_en . #1 BB_XTAL_AUXPLL_REF_CLK_EN_OVRD Override value for BB_XTAL_AUXPLL_REF_CLK_EN 25 1 read-write BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN Override control for BB_XTAL_AUXPLL_REF_CLK_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of BB_XTAL_AUXPLL_REF_CLK_EN_OVRD to override the signal bb_xtal_auxpll_ref_clk_en . #1 BB_XTAL_DAC_REF_CLK_EN_OVRD Override value for BB_XTAL_DAC_REF_CLK_EN 23 1 read-write BB_XTAL_DAC_REF_CLK_EN_OVRD_EN Override control for BB_XTAL_DAC_REF_CLK_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of BB_XTAL_DAC_REF_CLK_EN_OVRD to override the signal bb_xtal_dac_ref_clk_en . #1 BB_XTAL_PLL_REF_CLK_EN_OVRD Override value for BB_XTAL_PLL_REF_CLK_EN 21 1 read-write BB_XTAL_PLL_REF_CLK_EN_OVRD_EN Override control for BB_XTAL_PLL_REF_CLK_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of BB_XTAL_PLL_REF_CLK_EN_OVRD to override the signal bb_xtal_pll_ref_clk_en . #1 PLL_LOOP_IS_OPEN_OVRD Override value for PLL_LOOP_IS_OPEN 27 1 read-write PLL_LOOP_IS_OPEN_OVRD_EN Override control for PLL_LOOP_IS_OPEN 26 1 read-write 0 Normal operation. #0 1 Use the state of PLL_LOOP_IS_OPEN_OVRD to override the signal pll_loop_is_open . #1 SY_PD_CYCLE_SLIP_LD_EN_OVRD Override value for SY_PD_CYCLE_SLIP_LD_EN 29 1 read-write SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN Override control for SY_PD_CYCLE_SLIP_LD_EN 28 1 read-write 0 Normal operation. #0 1 Use the state of SY_PD_CYCLE_SLIP_LD_EN_OVRD to override the signal sy_pd_cycle_slip_ld_en . #1 SY_VCO_EN_OVRD Override value for SY_VCO_EN 31 1 read-write SY_VCO_EN_OVRD_EN Override control for SY_VCO_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of SY_VCO_EN_OVRD to override the signal sy_vco_en . #1 OVRD1 TSM OVERRIDE REGISTER 1 0x120 32 read-write n 0x0 0x0 RX_ADC_I_EN_OVRD Override value for RX_ADC_I_EN 23 1 read-write RX_ADC_I_EN_OVRD_EN Override control for RX_ADC_I_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of RX_ADC_I_EN_OVRD to override the signal rx_adc_i_en . #1 RX_ADC_Q_EN_OVRD Override value for RX_ADC_Q_EN 25 1 read-write RX_ADC_Q_EN_OVRD_EN Override control for RX_ADC_Q_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of RX_ADC_Q_EN_OVRD to override the signal rx_adc_q_en . #1 RX_ADC_RESET_EN_OVRD Override value for RX_ADC_RESET_EN 27 1 read-write RX_ADC_RESET_EN_OVRD_EN Override control for RX_ADC_RESET_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of RX_ADC_RESET_EN_OVRD to override the signal rx_adc_reset_en . #1 RX_BBA_I_EN_OVRD Override value for RX_BBA_I_EN 29 1 read-write RX_BBA_I_EN_OVRD_EN Override control for RX_BBA_I_EN 28 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_I_EN_OVRD to override the signal rx_bba_i_en . #1 RX_BBA_Q_EN_OVRD Override value for RX_BBA_Q_EN 31 1 read-write RX_BBA_Q_EN_OVRD_EN Override control for RX_BBA_Q_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_Q_EN_OVRD to override the signal rx_bba_q_en . #1 RX_MIXER_EN_OVRD Override value for RX_MIXER_EN 19 1 read-write RX_MIXER_EN_OVRD_EN Override control for RX_MIXER_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of RX_MIXER_EN_OVRD to override the signal rx_mixer_en . #1 SY_DIVN_CAL_EN_OVRD Override value for SY_DIVN_CAL_EN 17 1 read-write SY_DIVN_CAL_EN_OVRD_EN Override control for SY_DIVN_CAL_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of SY_DIVN_CAL_EN_OVRD to override the signal sy_divn_cal_en . #1 SY_DIVN_EN_OVRD Override value for SY_DIVN_EN 5 1 read-write SY_DIVN_EN_OVRD_EN Override control for SY_DIVN_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of SY_DIVN_EN_OVRD to override the signal sy_divn_en . #1 SY_LO_DIVN_EN_OVRD Override value for SY_LO_DIVN_EN 11 1 read-write SY_LO_DIVN_EN_OVRD_EN Override control for SY_LO_DIVN_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_DIVN_EN_OVRD to override the signal sy_lo_divn_en . #1 SY_LO_RX_BUF_EN_OVRD Override value for SY_LO_RX_BUF_EN 1 1 read-write SY_LO_RX_BUF_EN_OVRD_EN Override control for SY_LO_RX_BUF_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_RX_BUF_EN_OVRD to override the signal sy_lo_rx_buf_en . #1 SY_LO_RX_EN_OVRD Override value for SY_LO_RX_EN 13 1 read-write SY_LO_RX_EN_OVRD_EN Override control for SY_LO_RX_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_RX_EN_OVRD to override the signal sy_lo_rx_en . #1 SY_LO_TX_BUF_EN_OVRD Override value for SY_LO_TX_BUF_EN 3 1 read-write SY_LO_TX_BUF_EN_OVRD_EN Override control for SY_LO_TX_BUF_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_TX_BUF_EN_OVRD to override the signal sy_lo_tx_buf_en . #1 SY_LO_TX_EN_OVRD Override value for SY_LO_TX_EN 15 1 read-write SY_LO_TX_EN_OVRD_EN Override control for SY_LO_TX_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of SY_LO_TX_EN_OVRD to override the signal sy_lo_tx_en . #1 SY_PD_EN_OVRD Override value for SY_PD_EN 9 1 read-write SY_PD_EN_OVRD_EN Override control for SY_PD_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of SY_PD_EN_OVRD to override the signal sy_pd_en . #1 SY_PD_FILTER_CHARGE_EN_OVRD Override value for SY_PD_FILTER_CHARGE_EN 7 1 read-write SY_PD_FILTER_CHARGE_EN_OVRD_EN Override control for SY_PD_FILTER_CHARGE_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of SY_PD_FILTER_CHARGE_EN_OVRD to override the signal sy_pd_filter_charge_en . #1 TX_PA_EN_OVRD Override value for TX_PA_EN 21 1 read-write TX_PA_EN_OVRD_EN Override control for TX_PA_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of TX_PA_EN_OVRD to override the signal tx_pa_en . #1 OVRD2 TSM OVERRIDE REGISTER 2 0x124 32 read-write n 0x0 0x0 DCOC_EN_OVRD Override value for DCOC_EN 27 1 read-write DCOC_EN_OVRD_EN Override control for DCOC_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of DCOC_EN_OVRD to override the signal dcoc_en . #1 DCOC_INIT_OVRD Override value for DCOC_INIT 29 1 read-write DCOC_INIT_OVRD_EN Override control for DCOC_INIT 28 1 read-write 0 Normal operation. #0 1 Use the state of DCOC_INIT_OVRD to override the signal dcoc_init . #1 FREQ_TARG_LD_EN_OVRD Override value for FREQ_TARG_LD_EN 31 1 read-write FREQ_TARG_LD_EN_OVRD_EN Override control for FREQ_TARG_LD_EN 30 1 read-write 0 Normal operation. #0 1 Use the state of FREQ_TARG_LD_EN_OVRD to override the signal freq_targ_ld_en . #1 PLL_DIG_EN_OVRD Override value for PLL_DIG_EN 15 1 read-write PLL_DIG_EN_OVRD_EN Override control for PLL_DIG_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of PLL_DIG_EN_OVRD to override the signal pll_dig_en . #1 RX_BBA_DCOC_EN_OVRD Override value for RX_BBA_DCOC_EN 3 1 read-write RX_BBA_DCOC_EN_OVRD_EN Override control for RX_BBA_DCOC_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_DCOC_EN_OVRD to override the signal rx_bba_dcoc_en . #1 RX_BBA_PDET_EN_OVRD Override value for RX_BBA_PDET_EN 1 1 read-write RX_BBA_PDET_EN_OVRD_EN Override control for RX_BBA_PDET_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of RX_BBA_PDET_EN_OVRD to override the signal rx_bba_pdet_en . #1 RX_DIG_EN_OVRD Override value for RX_DIG_EN 19 1 read-write RX_DIG_EN_OVRD_EN Override control for RX_DIG_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of RX_DIG_EN_OVRD to override the signal rx_dig_en . #1 RX_INIT_OVRD Override value for RX_INIT 21 1 read-write RX_INIT_OVRD_EN Override control for RX_INIT 20 1 read-write 0 Normal operation. #0 1 Use the state of RX_INIT_OVRD to override the signal rx_init . #1 RX_LNA_EN_OVRD Override value for RX_LNA_EN 5 1 read-write RX_LNA_EN_OVRD_EN Override control for RX_LNA_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of RX_LNA_EN_OVRD to override the signal rx_lna_en . #1 RX_PHY_EN_OVRD Override value for RX_PHY_EN 25 1 read-write RX_PHY_EN_OVRD_EN Override control for RX_PHY_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of RX_PHY_EN_OVRD to override the signal rx_phy_en . #1 RX_TZA_DCOC_EN_OVRD Override control for RX_TZA_DCOC_EN 13 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_DCOC_EN_OVRD to override the signal rx_tza_dcoc_en . #1 RX_TZA_DCOC_EN_OVRD_EN Override control for RX_TZA_DCOC_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_DCOC_EN_OVRD to override the signal rx_tza_dcoc_en . #1 RX_TZA_I_EN_OVRD Override value for RX_TZA_I_EN 7 1 read-write RX_TZA_I_EN_OVRD_EN Override control for RX_TZA_I_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_I_EN_OVRD to override the signal rx_tza_i_en . #1 RX_TZA_PDET_EN_OVRD Override value for RX_TZA_PDET_EN 11 1 read-write RX_TZA_PDET_EN_OVRD_EN Override control for RX_TZA_PDET_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_PDET_EN_OVRD to override the signal rx_tza_pdet_en . #1 RX_TZA_Q_EN_OVRD Override value for RX_TZA_Q_EN 9 1 read-write RX_TZA_Q_EN_OVRD_EN Override control for RX_TZA_Q_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of RX_TZA_Q_EN_OVRD to override the signal rx_tza_q_en . #1 SIGMA_DELTA_EN_OVRD Override value for SIGMA_DELTA_EN 23 1 read-write SIGMA_DELTA_EN_OVRD_EN Override control for SIGMA_DELTA_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of SIGMA_DELTA_EN_OVRD to override the signal sigma_delta_en . #1 TX_DIG_EN_OVRD Override value for TX_DIG_EN 17 1 read-write TX_DIG_EN_OVRD_EN Override control for TX_DIG_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of TX_DIG_EN_OVRD to override the signal tx_dig_en . #1 OVRD3 TSM OVERRIDE REGISTER 3 0x128 32 read-write n 0x0 0x0 RXTX_AUXPLL_ADC_BUF_EN_OVRD Override value for RXTX_AUXPLL_ADC_BUF_EN 21 1 read-write RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN Override control for RXTX_AUXPLL_ADC_BUF_EN 20 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_ADC_BUF_EN_OVRD to override the signal rxtx_auxpll_adc_buf_en . #1 RXTX_AUXPLL_BIAS_EN_OVRD Override value for RXTX_AUXPLL_BIAS_EN 9 1 read-write RXTX_AUXPLL_BIAS_EN_OVRD_EN Override control for RXTX_AUXPLL_BIAS_EN 8 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_BIAS_EN_OVRD to override the signal rxtx_auxpll_bias_en . #1 RXTX_AUXPLL_DIG_BUF_EN_OVRD Override value for RXTX_AUXPLL_DIG_BUF_EN 23 1 read-write RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN Override control for RXTX_AUXPLL_DIG_BUF_EN 22 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_DIG_BUF_EN_OVRD to override the signal rxtx_auxpll_dig_buf_en . #1 RXTX_AUXPLL_FCAL_EN_OVRD Override value for RXTX_AUXPLL_FCAL_EN 13 1 read-write RXTX_AUXPLL_FCAL_EN_OVRD_EN Override control for RXTX_AUXPLL_FCAL_EN 12 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_FCAL_EN_OVRD to override the signal rxtx_auxpll_fcal_en . #1 RXTX_AUXPLL_LF_EN_OVRD Override value for RXTX_AUXPLL_LF_EN 15 1 read-write RXTX_AUXPLL_LF_EN_OVRD_EN Override control for RXTX_AUXPLL_LF_EN 14 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_LF_EN_OVRD to override the signal rxtx_auxpll_lf_en . #1 RXTX_AUXPLL_PD_EN_OVRD Override value for RXTX_AUXPLL_PD_EN 17 1 read-write RXTX_AUXPLL_PD_EN_OVRD_EN Override control for RXTX_AUXPLL_PD_EN 16 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_PD_EN_OVRD to override the signal rxtx_auxpll_pd_en . #1 RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD Override value for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN 19 1 read-write RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN Override control for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN 18 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD to override the signal rxtx_auxpll_pd_lf_filter_charge_en . #1 RXTX_AUXPLL_VCO_EN_OVRD Override value for RXTX_AUXPLL_VCO_EN 11 1 read-write RXTX_AUXPLL_VCO_EN_OVRD_EN Override control for RXTX_AUXPLL_VCO_EN 10 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_AUXPLL_VCO_EN_OVRD to override the signal rxtx_auxpll_vco_en . #1 RXTX_RCCAL_EN_OVRD Override value for RXTX_RCCAL_EN 25 1 read-write RXTX_RCCAL_EN_OVRD_EN Override control for RXTX_RCCAL_EN 24 1 read-write 0 Normal operation. #0 1 Use the state of RXTX_RCCAL_EN_OVRD to override the signal rxtx_rccal_en . #1 RX_MODE_OVRD Override value for RX_MODE 31 1 read-write RX_MODE_OVRD_EN Override control for RX_MODE 30 1 read-write 0 Normal operation. #0 1 Use the state of RX_MODE_OVRD to override the signal rx_mode . #1 TSM_SPARE0_EN_OVRD Override value for TSM_SPARE0_EN 1 1 read-write TSM_SPARE0_EN_OVRD_EN Override control for TSM_SPARE0_EN 0 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE0_EN_OVRD to override the signal tsm_spare0_en . #1 TSM_SPARE1_EN_OVRD Override value for TSM_SPARE1_EN 3 1 read-write TSM_SPARE1_EN_OVRD_EN Override control for TSM_SPARE1_EN 2 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE1_EN_OVRD to override the signal tsm_spare1_en . #1 TSM_SPARE2_EN_OVRD Override value for TSM_SPARE2_EN 5 1 read-write TSM_SPARE2_EN_OVRD_EN Override control for TSM_SPARE2_EN 4 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE2_EN_OVRD to override the signal tsm_spare2_en . #1 TSM_SPARE3_EN_OVRD Override value for TSM_SPARE3_EN 7 1 read-write TSM_SPARE3_EN_OVRD_EN Override control for TSM_SPARE3_EN 6 1 read-write 0 Normal operation. #0 1 Use the state of TSM_SPARE3_EN_OVRD to override the signal tsm_spare3_en . #1 TX_HPM_DAC_EN_OVRD Override value for TX_HPM_DAC_EN 27 1 read-write TX_HPM_DAC_EN_OVRD_EN Override control for TX_HPM_DAC_EN 26 1 read-write 0 Normal operation. #0 1 Use the state of TX_HPM_DAC_EN_OVRD to override the signal tx_hpm_dac_en . #1 TX_MODE_OVRD Override value for TX_MODE 29 1 read-write TX_MODE_OVRD_EN Override control for TX_MODE 28 1 read-write 0 Normal operation. #0 1 Use the state of TX_MODE_OVRD to override the signal tx_mode . #1 PA_POWER PA POWER 0x8 32 read-write n 0x0 0x0 PA_POWER PA POWER 0 6 read-write PA_RAMP_TBL0 PA RAMP TABLE 0 0xC 32 read-write n 0x0 0x0 PA_RAMP0 PA_RAMP0 0 6 read-write PA_RAMP1 PA_RAMP1 8 6 read-write PA_RAMP2 PA_RAMP2 16 6 read-write PA_RAMP3 PA_RAMP3 24 6 read-write PA_RAMP_TBL1 PA RAMP TABLE 1 0x10 32 read-write n 0x0 0x0 PA_RAMP4 PA_RAMP4 0 6 read-write PA_RAMP5 PA_RAMP5 8 6 read-write PA_RAMP6 PA_RAMP6 16 6 read-write PA_RAMP7 PA_RAMP7 24 6 read-write PA_RAMP_TBL2 PA RAMP TABLE 2 0x14 32 read-write n 0x0 0x0 PA_RAMP10 PA_RAMP10 16 6 read-write PA_RAMP11 PA_RAMP11 24 6 read-write PA_RAMP8 PA_RAMP8 0 6 read-write PA_RAMP9 PA_RAMP9 8 6 read-write PA_RAMP_TBL3 PA RAMP TABLE 3 0x18 32 read-write n 0x0 0x0 PA_RAMP12 PA_RAMP12 0 6 read-write PA_RAMP13 PA_RAMP13 8 6 read-write PA_RAMP14 PA_RAMP14 16 6 read-write PA_RAMP15 PA_RAMP15 24 6 read-write RECYCLE_COUNT TSM RECYCLE COUNT 0x24 32 read-write n 0x0 0x0 RECYCLE_COUNT0 TSM RX Recycle Count 0 0 8 read-write RECYCLE_COUNT1 TSM RX Recycle Count 1 8 8 read-write RECYCLE_COUNT2 TSM RX Recycle Count 2 16 8 read-write TIMING00 TSM_TIMING00 0x30 32 read-write n 0x0 0x0 BB_LDO_HF_EN_RX_HI Assertion time setting for BB_LDO_HF_EN (RX) 16 8 read-write BB_LDO_HF_EN_RX_LO De-assertion time setting for BB_LDO_HF_EN (RX) 24 8 read-write BB_LDO_HF_EN_TX_HI Assertion time setting for BB_LDO_HF_EN (TX) 0 8 read-write BB_LDO_HF_EN_TX_LO De-assertion time setting for BB_LDO_HF_EN (TX) 8 8 read-write TIMING01 TSM_TIMING01 0x34 32 read-write n 0x0 0x0 BB_LDO_ADCDAC_EN_RX_HI Assertion time setting for BB_LDO_ADCDAC_EN (RX) 16 8 read-write BB_LDO_ADCDAC_EN_RX_LO De-assertion time setting for BB_LDO_ADCDAC_EN (RX) 24 8 read-write BB_LDO_ADCDAC_EN_TX_HI Assertion time setting for BB_LDO_ADCDAC_EN (TX) 0 8 read-write BB_LDO_ADCDAC_EN_TX_LO De-assertion time setting for BB_LDO_ADCDAC_EN (TX) 8 8 read-write TIMING02 TSM_TIMING02 0x38 32 read-write n 0x0 0x0 BB_LDO_BBA_EN_RX_HI Assertion time setting for BB_LDO_BBA_EN (RX) 16 8 read-write BB_LDO_BBA_EN_RX_LO De-assertion time setting for BB_LDO_BBA_EN (RX) 24 8 read-write TIMING03 TSM_TIMING03 0x3C 32 read-write n 0x0 0x0 BB_LDO_PD_EN_RX_HI Assertion time setting for BB_LDO_PD_EN (RX) 16 8 read-write BB_LDO_PD_EN_RX_LO De-assertion time setting for BB_LDO_PD_EN (RX) 24 8 read-write BB_LDO_PD_EN_TX_HI Assertion time setting for BB_LDO_PD_EN (TX) 0 8 read-write BB_LDO_PD_EN_TX_LO De-assertion time setting for BB_LDO_PD_EN (TX) 8 8 read-write TIMING04 TSM_TIMING04 0x40 32 read-write n 0x0 0x0 BB_LDO_FDBK_EN_RX_HI Assertion time setting for BB_LDO_FDBK_EN (RX) 16 8 read-write BB_LDO_FDBK_EN_RX_LO De-assertion time setting for BB_LDO_FDBK_EN (RX) 24 8 read-write BB_LDO_FDBK_EN_TX_HI Assertion time setting for BB_LDO_FDBK_EN (TX) 0 8 read-write BB_LDO_FDBK_EN_TX_LO De-assertion time setting for BB_LDO_FDBK_EN (TX) 8 8 read-write TIMING05 TSM_TIMING05 0x44 32 read-write n 0x0 0x0 BB_LDO_VCOLO_EN_RX_HI Assertion time setting for BB_LDO_VCOLO_EN (RX) 16 8 read-write BB_LDO_VCOLO_EN_RX_LO De-assertion time setting for BB_LDO_VCOLO_EN (RX) 24 8 read-write BB_LDO_VCOLO_EN_TX_HI Assertion time setting for BB_LDO_VCOLO_EN (TX) 0 8 read-write BB_LDO_VCOLO_EN_TX_LO De-assertion time setting for BB_LDO_VCOLO_EN (TX) 8 8 read-write TIMING06 TSM_TIMING06 0x48 32 read-write n 0x0 0x0 BB_LDO_VTREF_EN_RX_HI Assertion time setting for BB_LDO_VTREF_EN (RX) 16 8 read-write BB_LDO_VTREF_EN_RX_LO De-assertion time setting for BB_LDO_VTREF_EN (RX) 24 8 read-write BB_LDO_VTREF_EN_TX_HI Assertion time setting for BB_LDO_VTREF_EN (TX) 0 8 read-write BB_LDO_VTREF_EN_TX_LO De-assertion time setting for BB_LDO_VTREF_EN (TX) 8 8 read-write TIMING07 TSM_TIMING07 0x4C 32 read-write n 0x0 0x0 BB_LDO_FDBK_BLEED_EN_RX_HI Assertion time setting for BB_LDO_FDBK_BLEED_EN (RX) 16 8 read-write BB_LDO_FDBK_BLEED_EN_RX_LO De-assertion time setting for BB_LDO_FDBK_BLEED_EN (RX) 24 8 read-write BB_LDO_FDBK_BLEED_EN_TX_HI Assertion time setting for BB_LDO_FDBK_BLEED_EN (TX) 0 8 read-write BB_LDO_FDBK_BLEED_EN_TX_LO De-assertion time setting for BB_LDO_FDBK_BLEED_EN (TX) 8 8 read-write TIMING08 TSM_TIMING08 0x50 32 read-write n 0x0 0x0 BB_LDO_VCOLO_BLEED_EN_RX_HI Assertion time setting for BB_LDO_VCOLO_BLEED_EN (RX) 16 8 read-write BB_LDO_VCOLO_BLEED_EN_RX_LO De-assertion time setting for BB_LDO_VCOLO_BLEED_EN (RX) 24 8 read-write BB_LDO_VCOLO_BLEED_EN_TX_HI Assertion time setting for BB_LDO_VCOLO_BLEED_EN (TX) 0 8 read-write BB_LDO_VCOLO_BLEED_EN_TX_LO De-assertion time setting for BB_LDO_VCOLO_BLEED_EN (TX) 8 8 read-write TIMING09 TSM_TIMING09 0x54 32 read-write n 0x0 0x0 BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI Assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (RX) 16 8 read-write BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO De-assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (RX) 24 8 read-write BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI Assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (TX) 0 8 read-write BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO De-assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (TX) 8 8 read-write TIMING10 TSM_TIMING10 0x58 32 read-write n 0x0 0x0 BB_XTAL_PLL_REF_CLK_EN_RX_HI Assertion time setting for BB_XTAL_PLL_REF_CLK_EN (RX) 16 8 read-write BB_XTAL_PLL_REF_CLK_EN_RX_LO De-assertion time setting for BB_XTAL_PLL_REF_CLK_EN (RX) 24 8 read-write BB_XTAL_PLL_REF_CLK_EN_TX_HI Assertion time setting for BB_XTAL_PLL_REF_CLK_EN (TX) 0 8 read-write BB_XTAL_PLL_REF_CLK_EN_TX_LO De-assertion time setting for BB_XTAL_PLL_REF_CLK_EN (TX) 8 8 read-write TIMING11 TSM_TIMING11 0x5C 32 read-write n 0x0 0x0 BB_XTAL_DAC_REF_CLK_EN_TX_HI Assertion time setting for BB_XTAL_DAC_REF_CLK_EN (TX) 0 8 read-write BB_XTAL_DAC_REF_CLK_EN_TX_LO De-assertion time setting for BB_XTAL_DAC_REF_CLK_EN (TX) 8 8 read-write TIMING12 TSM_TIMING12 0x60 32 read-write n 0x0 0x0 RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI Assertion time setting for RXTX_AUXPLL_VCO_REF_CLK_EN (RX) 16 8 read-write RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_VCO_REF_CLK_EN (RX) 24 8 read-write TIMING13 TSM_TIMING13 0x64 32 read-write n 0x0 0x0 PLL_LOOP_IS_OPEN_RX_HI Assertion time setting for PLL_LOOP_IS_OPEN (RX) 16 8 read-write PLL_LOOP_IS_OPEN_RX_LO De-assertion time setting for PLL_LOOP_IS_OPEN (RX) 24 8 read-write PLL_LOOP_IS_OPEN_TX_HI Assertion time setting for PLL_LOOP_IS_OPEN (TX) 0 8 read-write PLL_LOOP_IS_OPEN_TX_LO De-assertion time setting for PLL_LOOP_IS_OPEN (TX) 8 8 read-write TIMING14 TSM_TIMING14 0x68 32 read-write n 0x0 0x0 SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI Assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (RX) 16 8 read-write SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO De-assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (RX) 24 8 read-write SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI Assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (TX) 0 8 read-write SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO De-assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (TX) 8 8 read-write TIMING15 TSM_TIMING15 0x6C 32 read-write n 0x0 0x0 SY_VCO_EN_RX_HI Assertion time setting for SY_VCO_EN (RX) 16 8 read-write SY_VCO_EN_RX_LO De-assertion time setting for SY_VCO_EN (RX) 24 8 read-write SY_VCO_EN_TX_HI Assertion time setting for SY_VCO_EN (TX) 0 8 read-write SY_VCO_EN_TX_LO De-assertion time setting for SY_VCO_EN (TX) 8 8 read-write TIMING16 TSM_TIMING16 0x70 32 read-write n 0x0 0x0 SY_LO_RX_BUF_EN_RX_HI Assertion time setting for SY_LO_RX_BUF_EN (RX) 16 8 read-write SY_LO_RX_BUF_EN_RX_LO De-assertion time setting for SY_LO_RX_BUF_EN (RX) 24 8 read-write TIMING17 TSM_TIMING17 0x74 32 read-write n 0x0 0x0 SY_LO_TX_BUF_EN_TX_HI Assertion time setting for SY_LO_TX_BUF_EN (TX) 0 8 read-write SY_LO_TX_BUF_EN_TX_LO De-assertion time setting for SY_LO_TX_BUF_EN (TX) 8 8 read-write TIMING18 TSM_TIMING18 0x78 32 read-write n 0x0 0x0 SY_DIVN_EN_RX_HI Assertion time setting for SY_DIVN_EN (RX) 16 8 read-write SY_DIVN_EN_RX_LO De-assertion time setting for SY_DIVN_EN (RX) 24 8 read-write SY_DIVN_EN_TX_HI Assertion time setting for SY_DIVN_EN (TX) 0 8 read-write SY_DIVN_EN_TX_LO De-assertion time setting for SY_DIVN_EN (TX) 8 8 read-write TIMING19 TSM_TIMING19 0x7C 32 read-write n 0x0 0x0 SY_PD_FILTER_CHARGE_EN_RX_HI Assertion time setting for SY_PD_FILTER_CHARGE_EN (RX) 16 8 read-write SY_PD_FILTER_CHARGE_EN_RX_LO De-assertion time setting for SY_PD_FILTER_CHARGE_EN (RX) 24 8 read-write SY_PD_FILTER_CHARGE_EN_TX_HI Assertion time setting for SY_PD_FILTER_CHARGE_EN (TX) 0 8 read-write SY_PD_FILTER_CHARGE_EN_TX_LO De-assertion time setting for SY_PD_FILTER_CHARGE_EN (TX) 8 8 read-write TIMING20 TSM_TIMING20 0x80 32 read-write n 0x0 0x0 SY_PD_EN_RX_HI Assertion time setting for SY_PD_EN (RX) 16 8 read-write SY_PD_EN_RX_LO De-assertion time setting for SY_PD_EN (RX) 24 8 read-write SY_PD_EN_TX_HI Assertion time setting for SY_PD_EN (TX) 0 8 read-write SY_PD_EN_TX_LO De-assertion time setting for SY_PD_EN (TX) 8 8 read-write TIMING21 TSM_TIMING21 0x84 32 read-write n 0x0 0x0 SY_LO_DIVN_EN_RX_HI Assertion time setting for SY_LO_DIVN_EN (RX) 16 8 read-write SY_LO_DIVN_EN_RX_LO De-assertion time setting for SY_LO_DIVN_EN (RX) 24 8 read-write SY_LO_DIVN_EN_TX_HI Assertion time setting for SY_LO_DIVN_EN (TX) 0 8 read-write SY_LO_DIVN_EN_TX_LO De-assertion time setting for SY_LO_DIVN_EN (TX) 8 8 read-write TIMING22 TSM_TIMING22 0x88 32 read-write n 0x0 0x0 SY_LO_RX_EN_RX_HI Assertion time setting for SY_LO_RX_EN (RX) 16 8 read-write SY_LO_RX_EN_RX_LO De-assertion time setting for SY_LO_RX_EN (RX) 24 8 read-write TIMING23 TSM_TIMING23 0x8C 32 read-write n 0x0 0x0 SY_LO_TX_EN_TX_HI Assertion time setting for SY_LO_TX_EN (TX) 0 8 read-write SY_LO_TX_EN_TX_LO De-assertion time setting for SY_LO_TX_EN (TX) 8 8 read-write TIMING24 TSM_TIMING24 0x90 32 read-write n 0x0 0x0 SY_DIVN_CAL_EN_RX_HI Assertion time setting for SY_DIVN_CAL_EN (RX) 16 8 read-write SY_DIVN_CAL_EN_RX_LO De-assertion time setting for SY_DIVN_CAL_EN (RX) 24 8 read-write SY_DIVN_CAL_EN_TX_HI Assertion time setting for SY_DIVN_CAL_EN (TX) 0 8 read-write SY_DIVN_CAL_EN_TX_LO De-assertion time setting for SY_DIVN_CAL_EN (TX) 8 8 read-write TIMING25 TSM_TIMING25 0x94 32 read-write n 0x0 0x0 RX_LNA_MIXER_EN_RX_HI Assertion time setting for RX_LNA_MIXER_EN (RX) 16 8 read-write RX_LNA_MIXER_EN_RX_LO De-assertion time setting for RX_LNA_MIXER_EN (RX) 24 8 read-write TIMING26 TSM_TIMING26 0x98 32 read-write n 0x0 0x0 TX_PA_EN_TX_HI Assertion time setting for TX_PA_EN (TX) 0 8 read-write TX_PA_EN_TX_LO De-assertion time setting for TX_PA_EN (TX) 8 8 read-write TIMING27 TSM_TIMING27 0x9C 32 read-write n 0x0 0x0 RX_ADC_I_Q_EN_RX_HI Assertion time setting for RX_ADC_I_Q_EN (RX) 16 8 read-write RX_ADC_I_Q_EN_RX_LO De-assertion time setting for RX_ADC_I_Q_EN (RX) 24 8 read-write TIMING28 TSM_TIMING28 0xA0 32 read-write n 0x0 0x0 RX_ADC_RESET_EN_RX_HI Assertion time setting for RX_ADC_RESET_EN (RX) 16 8 read-write RX_ADC_RESET_EN_RX_LO De-assertion time setting for RX_ADC_RESET_EN (RX) 24 8 read-write TIMING29 TSM_TIMING29 0xA4 32 read-write n 0x0 0x0 RX_BBA_I_Q_EN_RX_HI Assertion time setting for RX_BBA_I_Q_EN (RX) 16 8 read-write RX_BBA_I_Q_EN_RX_LO De-assertion time setting for RX_BBA_I_Q_EN (RX) 24 8 read-write TIMING30 TSM_TIMING30 0xA8 32 read-write n 0x0 0x0 RX_BBA_PDET_EN_RX_HI Assertion time setting for RX_BBA_PDET_EN (RX) 16 8 read-write RX_BBA_PDET_EN_RX_LO De-assertion time setting for RX_BBA_PDET_EN (RX) 24 8 read-write TIMING31 TSM_TIMING31 0xAC 32 read-write n 0x0 0x0 RX_BBA_TZA_DCOC_EN_RX_HI Assertion time setting for RX_BBA_TZA_DCOC_EN (RX) 16 8 read-write RX_BBA_TZA_DCOC_EN_RX_LO De-assertion time setting for RX_BBA_TZA_DCOC_EN (RX) 24 8 read-write TIMING32 TSM_TIMING32 0xB0 32 read-write n 0x0 0x0 RX_TZA_I_Q_EN_RX_HI Assertion time setting for RX_TZA_I_Q_EN (RX) 16 8 read-write RX_TZA_I_Q_EN_RX_LO De-assertion time setting for RX_TZA_I_Q_EN (RX) 24 8 read-write TIMING33 TSM_TIMING33 0xB4 32 read-write n 0x0 0x0 RX_TZA_PDET_EN_RX_HI Assertion time setting for RX_TZA_PDET_EN (RX) 16 8 read-write RX_TZA_PDET_EN_RX_LO De-assertion time setting for RX_TZA_PDET_EN (RX) 24 8 read-write TIMING34 TSM_TIMING34 0xB8 32 read-write n 0x0 0x0 PLL_DIG_EN_RX_HI Assertion time setting for PLL_DIG_EN (RX) 16 8 read-write PLL_DIG_EN_RX_LO De-assertion time setting for PLL_DIG_EN (RX) 24 8 read-write PLL_DIG_EN_TX_HI Assertion time setting for PLL_DIG_EN (TX) 0 8 read-write PLL_DIG_EN_TX_LO De-assertion time setting for PLL_DIG_EN (TX) 8 8 read-write TIMING35 TSM_TIMING35 0xBC 32 read-write n 0x0 0x0 TX_DIG_EN_TX_HI Assertion time setting for TX_DIG_EN (TX) 0 8 read-write TX_DIG_EN_TX_LO De-assertion time setting for TX_DIG_EN (TX) 8 8 read-write TIMING36 TSM_TIMING36 0xC0 32 read-write n 0x0 0x0 RX_DIG_EN_RX_HI Assertion time setting for RX_DIG_EN (RX) 16 8 read-write RX_DIG_EN_RX_LO De-assertion time setting for RX_DIG_EN (RX) 24 8 read-write TIMING37 TSM_TIMING37 0xC4 32 read-write n 0x0 0x0 RX_INIT_RX_HI Assertion time setting for RX_INIT (RX) 16 8 read-write RX_INIT_RX_LO De-assertion time setting for RX_INIT (RX) 24 8 read-write TIMING38 TSM_TIMING38 0xC8 32 read-write n 0x0 0x0 SIGMA_DELTA_EN_RX_HI Assertion time setting for SIGMA_DELTA_EN (RX) 16 8 read-write SIGMA_DELTA_EN_RX_LO De-assertion time setting for SIGMA_DELTA_EN (RX) 24 8 read-write SIGMA_DELTA_EN_TX_HI Assertion time setting for SIGMA_DELTA_EN (TX) 0 8 read-write SIGMA_DELTA_EN_TX_LO De-assertion time setting for SIGMA_DELTA_EN (TX) 8 8 read-write TIMING39 TSM_TIMING39 0xCC 32 read-write n 0x0 0x0 RX_PHY_EN_RX_HI Assertion time setting for RX_PHY_EN (RX) 16 8 read-write RX_PHY_EN_RX_LO De-assertion time setting for RX_PHY_EN (RX) 24 8 read-write TIMING40 TSM_TIMING40 0xD0 32 read-write n 0x0 0x0 DCOC_EN_RX_HI Assertion time setting for DCOC_EN (RX) 16 8 read-write DCOC_EN_RX_LO De-assertion time setting for DCOC_EN (RX) 24 8 read-write TIMING41 TSM_TIMING41 0xD4 32 read-write n 0x0 0x0 DCOC_INIT_RX_HI Assertion time setting for DCOC_INIT (RX) 16 8 read-write DCOC_INIT_RX_LO De-assertion time setting for DCOC_INIT (RX) 24 8 read-write TIMING42 TSM_TIMING42 0xD8 32 read-write n 0x0 0x0 SAR_ADC_TRIG_EN_RX_HI Assertion time setting for SAR_ADC_TRIG_EN (RX) 16 8 read-write SAR_ADC_TRIG_EN_RX_LO De-assertion time setting for SAR_ADC_TRIG_EN (RX) 24 8 read-write SAR_ADC_TRIG_EN_TX_HI Assertion time setting for SAR_ADC_TRIG_EN (TX) 0 8 read-write SAR_ADC_TRIG_EN_TX_LO De-assertion time setting for SAR_ADC_TRIG_EN (TX) 8 8 read-write TIMING43 TSM_TIMING43 0xDC 32 read-write n 0x0 0x0 TSM_SPARE0_EN_RX_HI Assertion time setting for TSM_SPARE0_EN (RX) 16 8 read-write TSM_SPARE0_EN_RX_LO De-assertion time setting for TSM_SPARE0_EN (RX) 24 8 read-write TSM_SPARE0_EN_TX_HI Assertion time setting for TSM_SPARE0_EN (TX) 0 8 read-write TSM_SPARE0_EN_TX_LO De-assertion time setting for TSM_SPARE0_EN (TX) 8 8 read-write TIMING44 TSM_TIMING44 0xE0 32 read-write n 0x0 0x0 TSM_SPARE1_EN_RX_HI Assertion time setting for TSM_SPARE1_EN (RX) 16 8 read-write TSM_SPARE1_EN_RX_LO De-assertion time setting for TSM_SPARE1_EN (RX) 24 8 read-write TSM_SPARE1_EN_TX_HI Assertion time setting for TSM_SPARE1_EN (TX) 0 8 read-write TSM_SPARE1_EN_TX_LO De-assertion time setting for TSM_SPARE1_EN (TX) 8 8 read-write TIMING45 TSM_TIMING45 0xE4 32 read-write n 0x0 0x0 TSM_SPARE2_EN_RX_HI Assertion time setting for TSM_SPARE2_EN (RX) 16 8 read-write TSM_SPARE2_EN_RX_LO De-assertion time setting for TSM_SPARE2_EN (RX) 24 8 read-write TSM_SPARE2_EN_TX_HI Assertion time setting for TSM_SPARE2_EN (TX) 0 8 read-write TSM_SPARE2_EN_TX_LO De-assertion time setting for TSM_SPARE2_EN (TX) 8 8 read-write TIMING46 TSM_TIMING46 0xE8 32 read-write n 0x0 0x0 TSM_SPARE3_EN_RX_HI Assertion time setting for TSM_SPARE3_EN (RX) 16 8 read-write TSM_SPARE3_EN_RX_LO De-assertion time setting for TSM_SPARE3_EN (RX) 24 8 read-write TSM_SPARE3_EN_TX_HI Assertion time setting for TSM_SPARE3_EN (TX) 0 8 read-write TSM_SPARE3_EN_TX_LO De-assertion time setting for TSM_SPARE3_EN (TX) 8 8 read-write TIMING47 TSM_TIMING47 0xEC 32 read-write n 0x0 0x0 GPIO0_TRIG_EN_RX_HI Assertion time setting for GPIO0_TRIG_EN (RX) 16 8 read-write GPIO0_TRIG_EN_RX_LO De-assertion time setting for GPIO0_TRIG_EN (RX) 24 8 read-write GPIO0_TRIG_EN_TX_HI Assertion time setting for GPIO0_TRIG_EN (TX) 0 8 read-write GPIO0_TRIG_EN_TX_LO De-assertion time setting for GPIO0_TRIG_EN (TX) 8 8 read-write TIMING48 TSM_TIMING48 0xF0 32 read-write n 0x0 0x0 GPIO1_TRIG_EN_RX_HI Assertion time setting for GPIO1_TRIG_EN (RX) 16 8 read-write GPIO1_TRIG_EN_RX_LO De-assertion time setting for GPIO1_TRIG_EN (RX) 24 8 read-write GPIO1_TRIG_EN_TX_HI Assertion time setting for GPIO1_TRIG_EN (TX) 0 8 read-write GPIO1_TRIG_EN_TX_LO De-assertion time setting for GPIO1_TRIG_EN (TX) 8 8 read-write TIMING49 TSM_TIMING49 0xF4 32 read-write n 0x0 0x0 GPIO2_TRIG_EN_RX_HI Assertion time setting for GPIO2_TRIG_EN (RX) 16 8 read-write GPIO2_TRIG_EN_RX_LO De-assertion time setting for GPIO2_TRIG_EN (RX) 24 8 read-write GPIO2_TRIG_EN_TX_HI Assertion time setting for GPIO2_TRIG_EN (TX) 0 8 read-write GPIO2_TRIG_EN_TX_LO De-assertion time setting for GPIO2_TRIG_EN (TX) 8 8 read-write TIMING50 TSM_TIMING50 0xF8 32 read-write n 0x0 0x0 GPIO3_TRIG_EN_RX_HI Assertion time setting for GPIO3_TRIG_EN (RX) 16 8 read-write GPIO3_TRIG_EN_RX_LO De-assertion time setting for GPIO3_TRIG_EN (RX) 24 8 read-write GPIO3_TRIG_EN_TX_HI Assertion time setting for GPIO3_TRIG_EN (TX) 0 8 read-write GPIO3_TRIG_EN_TX_LO De-assertion time setting for GPIO3_TRIG_EN (TX) 8 8 read-write TIMING51 TSM_TIMING51 0xFC 32 read-write n 0x0 0x0 RXTX_AUXPLL_BIAS_EN_RX_HI Assertion time setting for RXTX_AUXPLL_BIAS_EN (RX) 16 8 read-write RXTX_AUXPLL_BIAS_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_BIAS_EN (RX) 24 8 read-write TIMING52 TSM_TIMING52 0x100 32 read-write n 0x0 0x0 RXTX_AUXPLL_FCAL_EN_RX_HI Assertion time setting for RXTX_AUXPLL_FCAL_EN (RX) 16 8 read-write RXTX_AUXPLL_FCAL_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_FCAL_EN (RX) 24 8 read-write TIMING53 TSM_TIMING53 0x104 32 read-write n 0x0 0x0 RXTX_AUXPLL_LF_PD_EN_RX_HI Assertion time setting for RXTX_AUXPLL_LF_PD_EN (RX) 16 8 read-write RXTX_AUXPLL_LF_PD_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_LF_PD_EN (RX) 24 8 read-write TIMING54 TSM_TIMING54 0x108 32 read-write n 0x0 0x0 RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI Assertion time setting for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN (RX) 16 8 read-write RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN (RX) 24 8 read-write TIMING55 TSM_TIMING55 0x10C 32 read-write n 0x0 0x0 RXTX_AUXPLL_ADC_BUF_EN_RX_HI Assertion time setting for RXTX_AUXPLL_ADC_BUF_EN (RX) 16 8 read-write RXTX_AUXPLL_ADC_BUF_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_ADC_BUF_EN (RX) 24 8 read-write TIMING56 TSM_TIMING56 0x110 32 read-write n 0x0 0x0 RXTX_AUXPLL_DIG_BUF_EN_RX_HI Assertion time setting for RXTX_AUXPLL_DIG_BUF_EN (RX) 16 8 read-write RXTX_AUXPLL_DIG_BUF_EN_RX_LO De-assertion time setting for RXTX_AUXPLL_DIG_BUF_EN (RX) 24 8 read-write TIMING57 TSM_TIMING57 0x114 32 read-write n 0x0 0x0 RXTX_RCCAL_EN_RX_HI Assertion time setting for RXTX_RCCAL_EN (RX) 16 8 read-write RXTX_RCCAL_EN_RX_LO De-assertion time setting for RXTX_RCCAL_EN (RX) 24 8 read-write TIMING58 TSM_TIMING58 0x118 32 read-write n 0x0 0x0 TX_HPM_DAC_EN_TX_HI Assertion time setting for TX_HPM_DAC_EN (TX) 0 8 read-write TX_HPM_DAC_EN_TX_LO De-assertion time setting for TX_HPM_DAC_EN (TX) 8 8 read-write XCVR_TX_DIG XCVR_TX_DIG XCVR_TX_DIG 0x0 0x0 0x1C registers n CTRL TX Digital Control 0x0 32 read-write n 0x0 0x0 DFT_CLK_SEL DFT Clock Selection 8 3 read-write 000 62.5 kHz #000 001 125 kHz #001 010 250 kHz #010 011 500 kHz #011 100 1 MHz #100 101 2 MHz #101 110 4 MHz #110 111 RF OSC Clock #111 FREQ_WORD_ADJ Frequency Word Adjustment 22 10 read-write LFSR_EN LFSR Enable 7 1 read-write LFSR_LENGTH LFSR Length 4 3 read-write 000 LFSR 9, tap mask 100010000 #000 001 LFSR 10, tap mask 1001000000 #001 010 LFSR 11, tap mask 11101000000 #010 011 LFSR 13, tap mask 1101100000000 #011 100 LFSR 15, tap mask 111010000000000 #100 101 LFSR 17, tap mask 11110000000000000 #101 RADIO_DFT_MODE Radio DFT Modes 0 4 read-write 0000 Normal Radio Operation, DFT not engaged. #0000 0001 Carrier Frequency Only #0001 0010 Pattern Register GFSK #0010 0011 LFSR GFSK #0011 0100 Pattern Register FSK #0100 0101 LFSR FSK #0101 0110 Pattern Register O-QPSK #0110 0111 LFSR O-QPSK #0111 1000 LFSR 802.15.4 Symbols #1000 1001 PLL Modulation from RAM #1001 1010 PLL Coarse Tune BIST #1010 1011 PLL Frequency Synthesizer BIST #1011 1100 High Port DAC BIST #1100 1101 VCO Frequency Meter #1101 SOC_TEST_SEL Radio Clock Selector for SoC RF Clock Tests 12 2 read-write 00 No Clock Selected #00 01 PLL Sigma Delta Clock, divided by 2 #01 10 Auxiliary PLL Clock, divided by 2 #10 11 RF Ref Osc clock, divided by 2 #11 TX_CAPTURE_POL Polarity of the Input Data for the Transmitter 16 1 read-write TX_DFT_EN DFT Modulation Enable 11 1 read-write ZERO_FDEV On-Air at Zero FDev 19 1 read-write DATA_PADDING TX Data Padding 0x4 32 read-write n 0x0 0x0 DATA_PADDING_PAT_0 Data Padding Pattern 0 0 8 read-write DATA_PADDING_PAT_1 Data Padding Pattern 1 8 8 read-write DFT_LFSR_OUT LFSR Output 16 15 read-only LRM LFSR Reset Mask 31 1 read-write DFT_PATTERN TX DFT Modulation Pattern 0x18 32 read-write n 0x0 0x0 DFT_MOD_PATTERN DFT Modulation Pattern 0 32 read-write FSK_SCALE TX FSK Modulation Levels 0x14 32 read-write n 0x0 0x0 FSK_BITRATE_SCALE_DISABLE FSK Bitrate Scaling Disable 31 1 read-write FSK_MODULATION_SCALE_0 FSK Modulation Scale for a data 0 0 13 read-write FSK_MODULATION_SCALE_1 FSK Modulation Scale for a data 1 16 13 read-write GFSK_COEFF1 TX GFSK Filter Coefficients 1 0x10 32 read-write n 0x0 0x0 GFSK_FILTER_COEFF_MANUAL1 GFSK Manual Filter Coefficient [31:0] 0 32 read-write GFSK_COEFF2 TX GFSK Filter Coefficients 2 0xC 32 read-write n 0x0 0x0 GFSK_FILTER_COEFF_MANUAL2 GFSK Manual Filter Coefficients[63:32] 0 32 read-write GFSK_CTRL TX GFSK Modulator Control 0x8 32 read-write n 0x0 0x0 GFSK_FLD Disable GFSK Filter Lookup Table 21 1 read-write GFSK_MI GFSK Modulation Index 16 2 read-write 00 0.32 #00 01 0.50 #01 10 0.70 #10 11 1.00 #11 GFSK_MLD Disable GFSK Multiply Lookup Table 20 1 read-write GFSK_MOD_INDEX_SCALING GFSK Modulation Index Scaling Factor 24 3 read-write 000 1 #000 001 1 + 1/32 #001 010 1 + 1/16 #010 011 1 + 1/8 #011 100 1 - 1/32 #100 101 1 - 1/16 #101 110 1 - 1/8 #110 GFSK_MULTIPLY_TABLE_MANUAL Manual GFSK Multiply Lookup Table Value 0 16 read-write TX_IMAGE_FILTER_0_OVRD TX Image Filter 0 Override Control 29 1 read-write TX_IMAGE_FILTER_1_OVRD TX Image Filter 1 Override Control 30 1 read-write TX_IMAGE_FILTER_2_OVRD TX Image Filter 2 Override Control 31 1 read-write TX_IMAGE_FILTER_OVRD_EN TX Image Filter Override Enable 28 1 read-write